/* don't suspend or resume card normally */
                dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 
-               pci_set_power_state(dev->pdev, PCI_D0);
-               amdgpu_device_load_pci_state(dev->pdev);
-               r = pci_enable_device(dev->pdev);
+               pci_set_power_state(pdev, PCI_D0);
+               amdgpu_device_load_pci_state(pdev);
+               r = pci_enable_device(pdev);
                if (r)
                        DRM_WARN("pci_enable_device failed (%d)\n", r);
                amdgpu_device_resume(dev, true);
                drm_kms_helper_poll_disable(dev);
                dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
                amdgpu_device_suspend(dev, true);
-               amdgpu_device_cache_pci_state(dev->pdev);
+               amdgpu_device_cache_pci_state(pdev);
                /* Shut down the device */
-               pci_disable_device(dev->pdev);
-               pci_set_power_state(dev->pdev, PCI_D3cold);
+               pci_disable_device(pdev);
+               pci_set_power_state(pdev, PCI_D3cold);
                dev->switch_power_state = DRM_SWITCH_POWER_OFF;
        }
 }
        adev->enable_virtual_display = false;
 
        if (amdgpu_virtual_display) {
-               struct drm_device *ddev = adev_to_drm(adev);
-               const char *pci_address_name = pci_name(ddev->pdev);
+               const char *pci_address_name = pci_name(adev->pdev);
                char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
 
                pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
                }
        }
 
-       pci_enable_pcie_error_reporting(adev->ddev.pdev);
+       pci_enable_pcie_error_reporting(adev->pdev);
 
        /* Post card if necessary */
        if (amdgpu_device_need_post(adev)) {
 
                                       struct drm_file *file_priv,
                                       const struct drm_mode_fb_cmd2 *mode_cmd)
 {
+       struct amdgpu_device *adev = drm_to_adev(dev);
        struct drm_gem_object *obj;
        struct amdgpu_framebuffer *amdgpu_fb;
        int ret;
 
        if (ret)
                return ret;
 
-       ddev->pdev = pdev;
        pci_set_drvdata(pdev, ddev);
 
        ret = amdgpu_driver_load_kms(adev, ent->driver_data);
 
        DRM_INFO("fb depth is %d\n", fb->format->depth);
        DRM_INFO("   pitch is %d\n", fb->pitches[0]);
 
-       vga_switcheroo_client_fb_set(adev_to_drm(adev)->pdev, info);
+       vga_switcheroo_client_fb_set(adev->pdev, info);
        return 0;
 
 out:
 
        int r = 0;
 
        if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
-               dev_dbg(&dev->pdev->dev,
+               dev_dbg(dev->dev,
                        "va_address 0x%LX is in reserved area 0x%LX\n",
                        args->va_address, AMDGPU_VA_RESERVED_SIZE);
                return -EINVAL;
 
        if (args->va_address >= AMDGPU_GMC_HOLE_START &&
            args->va_address < AMDGPU_GMC_HOLE_END) {
-               dev_dbg(&dev->pdev->dev,
+               dev_dbg(dev->dev,
                        "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
                        args->va_address, AMDGPU_GMC_HOLE_START,
                        AMDGPU_GMC_HOLE_END);
        vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
        vm_size -= AMDGPU_VA_RESERVED_SIZE;
        if (args->va_address + args->map_size > vm_size) {
-               dev_dbg(&dev->pdev->dev,
+               dev_dbg(dev->dev,
                        "va_address 0x%llx is in top reserved area 0x%llx\n",
                        args->va_address + args->map_size, vm_size);
                return -EINVAL;
        }
 
        if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
-               dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
+               dev_dbg(dev->dev, "invalid flags combination 0x%08X\n",
                        args->flags);
                return -EINVAL;
        }
        case AMDGPU_VA_OP_REPLACE:
                break;
        default:
-               dev_dbg(&dev->pdev->dev, "unsupported operation %d\n",
+               dev_dbg(dev->dev, "unsupported operation %d\n",
                        args->operation);
                return -EINVAL;
        }
 
        i2c->rec = *rec;
        i2c->adapter.owner = THIS_MODULE;
        i2c->adapter.class = I2C_CLASS_DDC;
-       i2c->adapter.dev.parent = &dev->pdev->dev;
+       i2c->adapter.dev.parent = dev->dev;
        i2c->dev = dev;
        i2c_set_adapdata(&i2c->adapter, i2c);
        mutex_init(&i2c->mutex);
 
            (amdgpu_is_atpx_hybrid() ||
             amdgpu_has_atpx_dgpu_power_cntl()) &&
            ((flags & AMD_IS_APU) == 0) &&
-           !pci_is_thunderbolt_attached(dev->pdev))
+           !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
                flags |= AMD_IS_PX;
 
        parent = pci_upstream_bridge(adev->pdev);
         */
        r = amdgpu_device_init(adev, flags);
        if (r) {
-               dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
+               dev_err(dev->dev, "Fatal error during GPU init\n");
                goto out;
        }
 
 
        acpi_status = amdgpu_acpi_init(adev);
        if (acpi_status)
-               dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
+               dev_dbg(dev->dev, "Error during ACPI methods call\n");
 
        if (adev->runpm) {
                /* only need to skip on ATPX */
                if (!dev_info)
                        return -ENOMEM;
 
-               dev_info->device_id = dev->pdev->device;
+               dev_info->device_id = adev->pdev->device;
                dev_info->chip_rev = adev->rev_id;
                dev_info->external_rev = adev->external_rev_id;
-               dev_info->pci_rev = dev->pdev->revision;
+               dev_info->pci_rev = adev->pdev->revision;
                dev_info->family = adev->family;
                dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
                dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;