const struct aq_fw_ops *aq_fw_ops;
        void __iomem *mmio;
        struct aq_hw_link_status_s aq_link_status;
-       struct hw_aq_atl_utils_mbox mbox;
+       struct hw_atl_utils_mbox mbox;
        struct hw_atl_stats_s last_stats;
        struct aq_stats_s curr_stats;
        u64 speed;
        u32 mbox_addr;
        u32 rpc_addr;
        u32 rpc_tid;
-       struct hw_aq_atl_utils_fw_rpc rpc;
+       struct hw_atl_utils_fw_rpc rpc;
 };
 
 struct aq_ring_s;
 
 const struct aq_hw_caps_s hw_atl_a0_caps_aqc100 = {
        DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
        .media_type = AQ_HW_MEDIA_TYPE_FIBRE,
-       .link_speed_msk = HW_ATL_A0_RATE_5G |
-                         HW_ATL_A0_RATE_2G5 |
-                         HW_ATL_A0_RATE_1G |
-                         HW_ATL_A0_RATE_100M,
+       .link_speed_msk = AQ_NIC_RATE_5G |
+                         AQ_NIC_RATE_2GS |
+                         AQ_NIC_RATE_1G |
+                         AQ_NIC_RATE_100M,
 };
 
 const struct aq_hw_caps_s hw_atl_a0_caps_aqc107 = {
        DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
        .media_type = AQ_HW_MEDIA_TYPE_TP,
-       .link_speed_msk = HW_ATL_A0_RATE_10G |
-                         HW_ATL_A0_RATE_5G |
-                         HW_ATL_A0_RATE_2G5 |
-                         HW_ATL_A0_RATE_1G |
-                         HW_ATL_A0_RATE_100M,
+       .link_speed_msk = AQ_NIC_RATE_10G |
+                         AQ_NIC_RATE_5G |
+                         AQ_NIC_RATE_2GS |
+                         AQ_NIC_RATE_1G |
+                         AQ_NIC_RATE_100M,
 };
 
 const struct aq_hw_caps_s hw_atl_a0_caps_aqc108 = {
        DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
        .media_type = AQ_HW_MEDIA_TYPE_TP,
-       .link_speed_msk = HW_ATL_A0_RATE_5G  |
-                         HW_ATL_A0_RATE_2G5 |
-                         HW_ATL_A0_RATE_1G  |
-                         HW_ATL_A0_RATE_100M,
+       .link_speed_msk = AQ_NIC_RATE_5G |
+                         AQ_NIC_RATE_2GS |
+                         AQ_NIC_RATE_1G |
+                         AQ_NIC_RATE_100M,
 };
 
 const struct aq_hw_caps_s hw_atl_a0_caps_aqc109 = {
        DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
        .media_type = AQ_HW_MEDIA_TYPE_TP,
-       .link_speed_msk = HW_ATL_A0_RATE_2G5 |
-                         HW_ATL_A0_RATE_1G |
-                         HW_ATL_A0_RATE_100M,
+       .link_speed_msk = AQ_NIC_RATE_2GS |
+                         AQ_NIC_RATE_1G |
+                         AQ_NIC_RATE_100M,
 };
 
 static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
 
 #define HW_ATL_A0_MPI_SPEED_MSK       0xFFFFU
 #define HW_ATL_A0_MPI_SPEED_SHIFT     16U
 
-#define HW_ATL_A0_RATE_10G            BIT(0)
-#define HW_ATL_A0_RATE_5G             BIT(1)
-#define HW_ATL_A0_RATE_2G5            BIT(3)
-#define HW_ATL_A0_RATE_1G             BIT(4)
-#define HW_ATL_A0_RATE_100M           BIT(5)
-
 #define HW_ATL_A0_TXBUF_MAX 160U
 #define HW_ATL_A0_RXBUF_MAX 320U
 
 
 const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = {
        DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
        .media_type = AQ_HW_MEDIA_TYPE_FIBRE,
-       .link_speed_msk = HW_ATL_B0_RATE_10G |
-                         HW_ATL_B0_RATE_5G |
-                         HW_ATL_B0_RATE_2G5 |
-                         HW_ATL_B0_RATE_1G |
-                         HW_ATL_B0_RATE_100M,
+       .link_speed_msk = AQ_NIC_RATE_10G |
+                         AQ_NIC_RATE_5G |
+                         AQ_NIC_RATE_2GS |
+                         AQ_NIC_RATE_1G |
+                         AQ_NIC_RATE_100M,
 };
 
 const struct aq_hw_caps_s hw_atl_b0_caps_aqc107 = {
        DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
        .media_type = AQ_HW_MEDIA_TYPE_TP,
-       .link_speed_msk = HW_ATL_B0_RATE_10G |
-                         HW_ATL_B0_RATE_5G |
-                         HW_ATL_B0_RATE_2G5 |
-                         HW_ATL_B0_RATE_1G |
-                         HW_ATL_B0_RATE_100M,
+       .link_speed_msk = AQ_NIC_RATE_10G |
+                         AQ_NIC_RATE_5G |
+                         AQ_NIC_RATE_2GS |
+                         AQ_NIC_RATE_1G |
+                         AQ_NIC_RATE_100M,
 };
 
 const struct aq_hw_caps_s hw_atl_b0_caps_aqc108 = {
        DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
        .media_type = AQ_HW_MEDIA_TYPE_TP,
-       .link_speed_msk = HW_ATL_B0_RATE_5G |
-                         HW_ATL_B0_RATE_2G5 |
-                         HW_ATL_B0_RATE_1G |
-                         HW_ATL_B0_RATE_100M,
+       .link_speed_msk = AQ_NIC_RATE_5G |
+                         AQ_NIC_RATE_2GS |
+                         AQ_NIC_RATE_1G |
+                         AQ_NIC_RATE_100M,
 };
 
 const struct aq_hw_caps_s hw_atl_b0_caps_aqc109 = {
        DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
        .media_type = AQ_HW_MEDIA_TYPE_TP,
-       .link_speed_msk = HW_ATL_B0_RATE_2G5 |
-                         HW_ATL_B0_RATE_1G |
-                         HW_ATL_B0_RATE_100M,
+       .link_speed_msk = AQ_NIC_RATE_2GS |
+                         AQ_NIC_RATE_1G |
+                         AQ_NIC_RATE_100M,
 };
 
 static int hw_atl_b0_hw_reset(struct aq_hw_s *self)
 
 #define HW_ATL_B0_MPI_SPEED_MSK         0xFFFFU
 #define HW_ATL_B0_MPI_SPEED_SHIFT       16U
 
-#define HW_ATL_B0_RATE_10G              BIT(0)
-#define HW_ATL_B0_RATE_5G               BIT(1)
-#define HW_ATL_B0_RATE_2G5              BIT(3)
-#define HW_ATL_B0_RATE_1G               BIT(4)
-#define HW_ATL_B0_RATE_100M             BIT(5)
-
 #define HW_ATL_B0_TXBUF_MAX  160U
 #define HW_ATL_B0_RXBUF_MAX  320U
 
 
 }
 
 int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
-                            struct hw_aq_atl_utils_fw_rpc **rpc)
+                            struct hw_atl_utils_fw_rpc **rpc)
 {
        int err = 0;
        struct aq_hw_atl_utils_fw_rpc_tid_s sw;
 }
 
 int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
-                              struct hw_aq_atl_utils_mbox_header *pmbox)
+                              struct hw_atl_utils_mbox_header *pmbox)
 {
        return hw_atl_utils_fw_downld_dwords(self,
                                             self->mbox_addr,
 }
 
 void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
-                                struct hw_aq_atl_utils_mbox *pmbox)
+                                struct hw_atl_utils_mbox *pmbox)
 {
        int err = 0;
 
 {
        int err = 0;
        u32 transaction_id = 0;
-       struct hw_aq_atl_utils_mbox_header mbox;
+       struct hw_atl_utils_mbox_header mbox;
        u32 val = aq_hw_read_reg(self, HW_ATL_MPI_CONTROL_ADR);
 
        if (state == MPI_RESET) {
 
 int hw_atl_utils_update_stats(struct aq_hw_s *self)
 {
-       struct hw_aq_atl_utils_mbox mbox;
+       struct hw_atl_utils_mbox mbox;
 
        hw_atl_utils_mpi_read_stats(self, &mbox);
 
 
 static int aq_fw1x_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac)
 {
-       struct hw_aq_atl_utils_fw_rpc *prpc = NULL;
+       struct hw_atl_utils_fw_rpc *prpc = NULL;
        unsigned int rpc_size = 0U;
        int err = 0;
 
 int aq_fw1x_set_power(struct aq_hw_s *self, unsigned int power_state,
                      u8 *mac)
 {
-       struct hw_aq_atl_utils_fw_rpc *prpc = NULL;
+       struct hw_atl_utils_fw_rpc *prpc = NULL;
        unsigned int rpc_size = 0U;
        int err = 0;
 
 
        } v4;
 };
 
-struct __packed hw_aq_atl_utils_fw_rpc {
+struct __packed hw_atl_utils_fw_rpc {
        u32 msg_id;
 
        union {
        };
 };
 
-struct __packed hw_aq_atl_utils_mbox_header {
+struct __packed hw_atl_utils_mbox_header {
        u32 version;
        u32 transaction_id;
        u32 error;
        u32 caps_hi;
 };
 
-struct __packed hw_aq_atl_utils_mbox {
-       struct hw_aq_atl_utils_mbox_header header;
+struct __packed hw_atl_utils_mbox {
+       struct hw_atl_utils_mbox_header header;
        struct hw_atl_stats_s stats;
        struct hw_aq_info info;
 };
 void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p);
 
 int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
-                              struct hw_aq_atl_utils_mbox_header *pmbox);
+                              struct hw_atl_utils_mbox_header *pmbox);
 
 void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
-                                struct hw_aq_atl_utils_mbox *pmbox);
+                                struct hw_atl_utils_mbox *pmbox);
 
 void hw_atl_utils_mpi_set(struct aq_hw_s *self,
                          enum hal_atl_utils_fw_state_e state,
 int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size);
 
 int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
-                            struct hw_aq_atl_utils_fw_rpc **rpc);
+                            struct hw_atl_utils_fw_rpc **rpc);
 
 extern const struct aq_fw_ops aq_fw_1x_ops;
 extern const struct aq_fw_ops aq_fw_2x_ops;
 
 
 static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self, u8 *mac)
 {
-       struct hw_aq_atl_utils_fw_rpc *rpc = NULL;
+       struct hw_atl_utils_fw_rpc *rpc = NULL;
        struct offload_info *cfg = NULL;
        unsigned int rpc_size = 0U;
        u32 mpi_opts;
 
 static int aq_fw2x_set_wol_params(struct aq_hw_s *self, u8 *mac)
 {
-       struct hw_aq_atl_utils_fw_rpc *rpc = NULL;
+       struct hw_atl_utils_fw_rpc *rpc = NULL;
        struct fw2x_msg_wol *msg = NULL;
        u32 mpi_opts;
        int err = 0;
        u32 mpi_state;
        u32 caps_hi;
        int err = 0;
-       u32 addr = self->mbox_addr + offsetof(struct hw_aq_atl_utils_mbox, info) +
+       u32 addr = self->mbox_addr + offsetof(struct hw_atl_utils_mbox, info) +
                   offsetof(struct hw_aq_info, caps_hi);
 
        err = hw_atl_utils_fw_downld_dwords(self, addr, &caps_hi,