perf/x86/intel/uncore: Update Ice Lake uncore units

There are some updates for the Icelake model specific uncore performance
monitors. (The update can be found at 10th generation intel core
processors families specification update Revision 004, ICL068)

1) Counter 0 of ARB uncore unit is not available for software use
2) The global 'enable bit' (bit 29) and 'freeze bit' (bit 31) of
   MSR_UNC_PERF_GLOBAL_CTRL cannot be used to control counter behavior.
   Needs to use local enable in event select MSR.

Accessing the modified bit/registers will be ignored by HW. Users may
observe inaccurate results with the current code.

The changes of the MSR_UNC_PERF_GLOBAL_CTRL imply that groups cannot be
read atomically anymore. Although the error of the result for a group
becomes a bit bigger, it still far lower than not using a group. The
group support is still kept. Only Remove the *_box() related
implementation.

Since the counter 0 of ARB uncore unit is not available, update the MSR
address for the ARB uncore unit.

There is no change for IMC uncore unit, which only include free-running
counters.

Fixes: 6e394376ee89 ("perf/x86/intel/uncore: Add Intel Icelake uncore support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200925134905.8839-2-kan.liang@linux.intel.com

diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c
index d2d43b6d6946b93bcecd8512b2002f24b3e4593d..2bdfcf80b4340e599d96536760f5f360670afddc 100644 (file)
--- a/arch/x86/events/intel/uncore_snb.c
+++ b/arch/x86/events/intel/uncore_snb.c
@@ -126,6 +126,10 @@
 #define ICL_UNC_CBO_0_PER_CTR0                 0x702
 #define ICL_UNC_CBO_MSR_OFFSET                 0x8
 
+/* ICL ARB register */
+#define ICL_UNC_ARB_PER_CTR                    0x3b1
+#define ICL_UNC_ARB_PERFEVTSEL                 0x3b3
+
 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
 DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
@@ -313,6 +317,12 @@ void skl_uncore_cpu_init(void)
        snb_uncore_arb.ops = &skl_uncore_msr_ops;
 }
 
+static struct intel_uncore_ops icl_uncore_msr_ops = {
+       .disable_event  = snb_uncore_msr_disable_event,
+       .enable_event   = snb_uncore_msr_enable_event,
+       .read_counter   = uncore_msr_read_counter,
+};
+
 static struct intel_uncore_type icl_uncore_cbox = {
        .name           = "cbox",
        .num_counters   = 4,
@@ -321,7 +331,7 @@ static struct intel_uncore_type icl_uncore_cbox = {
        .event_ctl      = SNB_UNC_CBO_0_PERFEVTSEL0,
        .event_mask     = SNB_UNC_RAW_EVENT_MASK,
        .msr_offset     = ICL_UNC_CBO_MSR_OFFSET,
-       .ops            = &skl_uncore_msr_ops,
+       .ops            = &icl_uncore_msr_ops,
        .format_group   = &snb_uncore_format_group,
 };
 
@@ -350,13 +360,25 @@ static struct intel_uncore_type icl_uncore_clockbox = {
        .single_fixed   = 1,
        .event_mask     = SNB_UNC_CTL_EV_SEL_MASK,
        .format_group   = &icl_uncore_clock_format_group,
-       .ops            = &skl_uncore_msr_ops,
+       .ops            = &icl_uncore_msr_ops,
        .event_descs    = icl_uncore_events,
 };
 
+static struct intel_uncore_type icl_uncore_arb = {
+       .name           = "arb",
+       .num_counters   = 1,
+       .num_boxes      = 1,
+       .perf_ctr_bits  = 44,
+       .perf_ctr       = ICL_UNC_ARB_PER_CTR,
+       .event_ctl      = ICL_UNC_ARB_PERFEVTSEL,
+       .event_mask     = SNB_UNC_RAW_EVENT_MASK,
+       .ops            = &icl_uncore_msr_ops,
+       .format_group   = &snb_uncore_format_group,
+};
+
 static struct intel_uncore_type *icl_msr_uncores[] = {
        &icl_uncore_cbox,
-       &snb_uncore_arb,
+       &icl_uncore_arb,
        &icl_uncore_clockbox,
        NULL,
 };
@@ -374,7 +396,6 @@ void icl_uncore_cpu_init(void)
 {
        uncore_msr_uncores = icl_msr_uncores;
        icl_uncore_cbox.num_boxes = icl_get_cbox_num();
-       snb_uncore_arb.ops = &skl_uncore_msr_ops;
 }
 
 static struct intel_uncore_type *tgl_msr_uncores[] = {