drm/amdgpu: Use correct SRIOV macro for gmc_v9_0_vm_fault_interrupt_state

Under SRIOV, programming to VM_CONTEXT*_CNTL regs failed because the
current macro does not pass through the correct xcc instance.
Use the *REG32_XCC macro in this case.

The behaviour without SRIOV is the same without this patch.

Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Reviewed-by: Zhigang Luo <Zhigang.Luo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index d442ae85162db5ff8c269969efa4b9c963d33382..1439e62e9378d350a880651ba30738dab74b9800 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -496,14 +496,14 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
                                if (j >= AMDGPU_MMHUB0(0))
                                        tmp = RREG32_SOC15_IP(MMHUB, reg);
                                else
-                                       tmp = RREG32_SOC15_IP(GC, reg);
+                                       tmp = RREG32_XCC(reg, j);
 
                                tmp &= ~bits;
 
                                if (j >= AMDGPU_MMHUB0(0))
                                        WREG32_SOC15_IP(MMHUB, reg, tmp);
                                else
-                                       WREG32_SOC15_IP(GC, reg, tmp);
+                                       WREG32_XCC(reg, tmp, j);
                        }
                }
                break;
@@ -524,14 +524,14 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
                                if (j >= AMDGPU_MMHUB0(0))
                                        tmp = RREG32_SOC15_IP(MMHUB, reg);
                                else
-                                       tmp = RREG32_SOC15_IP(GC, reg);
+                                       tmp = RREG32_XCC(reg, j);
 
                                tmp |= bits;
 
                                if (j >= AMDGPU_MMHUB0(0))
                                        WREG32_SOC15_IP(MMHUB, reg, tmp);
                                else
-                                       WREG32_SOC15_IP(GC, reg, tmp);
+                                       WREG32_XCC(reg, tmp, j);
                        }
                }
                break;