clk[IMX6QDL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
        clk[IMX6QDL_CLK_TWD]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
        clk[IMX6QDL_CLK_GPT_3M]    = imx_clk_fixed_factor("gpt_3m",    "osc",            1, 8);
+       clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
        if (cpu_is_imx6dl()) {
                clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
                clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
 
 #define IMX6QDL_PLL6_BYPASS                    235
 #define IMX6QDL_PLL7_BYPASS                    236
 #define IMX6QDL_CLK_GPT_3M                     237
-#define IMX6QDL_CLK_END                                238
+#define IMX6QDL_CLK_VIDEO_27M                  238
+#define IMX6QDL_CLK_END                                239
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */