uint32_t asic_blank_end;
        uint32_t v_init;
        uint32_t v_fp2 = 0;
-       int32_t vertical_line_start;
 
        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 
                        patched_crtc_timing.v_border_top;
 
        /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */
-       vertical_line_start = asic_blank_end - optc1->vstartup_start + 1;
-       if (vertical_line_start < 0)
-               v_fp2 = -vertical_line_start;
+       if (optc1->vstartup_start > asic_blank_end)
+               v_fp2 = optc1->vstartup_start - asic_blank_end;
 
        /* Interlace */
        if (REG(OTG_INTERLACE_CONTROL)) {
 
        .xfc_supported = true,
        .xfc_fill_bw_overhead_percent = 10.0,
        .xfc_fill_constant_bytes = 0,
+       .number_of_cursors = 1,
 };
 
 struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
        .xfc_supported = true,
        .xfc_fill_bw_overhead_percent = 10.0,
        .xfc_fill_constant_bytes = 0,
-       .ptoi_supported = 0
+       .ptoi_supported = 0,
+       .number_of_cursors = 1,
 };
 
 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
                /* todo: default max for now, until there is logic reflecting this in dc*/
                pipes[pipe_cnt].dout.output_bpc = 12;
                /*
-                * Use max cursor settings for calculations to minimize
+                * For graphic plane, cursor number is 1, nv12 is 0
                 * bw calculations due to cursor on/off
                 */
-               pipes[pipe_cnt].pipe.src.num_cursors = 2;
+               if (res_ctx->pipe_ctx[i].plane_state &&
+                               res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+                       pipes[pipe_cnt].pipe.src.num_cursors = 0;
+               else
+                       pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
+
                pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
                pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
-               pipes[pipe_cnt].pipe.src.cur1_src_width = 256;
-               pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
 
                if (!res_ctx->pipe_ctx[i].plane_state) {
                        pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;