drm/amd/display: disable forced stutter disable after programming watermark

vbios will disable stutter pre-OS.  driver re-enable after programming watermark

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
index da2f99dcd76654fecb899c771503cb67e85bf141..3e3fcf2395ae321705efe3e17bc0a377f2a707c8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
@@ -582,6 +582,7 @@ static void program_watermarks(
                unsigned int refclk_mhz)
 {
        struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+       uint32_t force_en = mem_input->ctx->dc->debug.disable_stutter ? 1 : 0;
        /*
         * Need to clamp to max of the register values (i.e. no wrap)
         * for dcn1, all wm registers are 21-bit wide
@@ -793,6 +794,10 @@ static void program_watermarks(
        REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
                        DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
 
+       REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
+                       DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
+                       DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
+
 #if 0
        REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
                        DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
index 48b313b213c07009a35a348377c1f801e0c02014..37683d072b421e5526a414c0405fc3f1d943bce1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
@@ -127,6 +127,7 @@
        SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D),\
        SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
        SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
+       SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
        SR(DCHUBBUB_ARB_SAT_LEVEL),\
        SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
        /* todo:  get these from GVM instead of reading registers ourselves */\
@@ -239,6 +240,7 @@ struct dcn_mi_registers {
        uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
        uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
        uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
+       uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
        uint32_t DCHUBBUB_ARB_SAT_LEVEL;
        uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
 
@@ -381,6 +383,8 @@ struct dcn_mi_registers {
        MI_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh),\
        MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh),\
        MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh),\
+       MI_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh),\
+       MI_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh),\
        MI_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh),\
        MI_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh),\
        /* todo:  get these from GVM instead of reading registers ourselves */\
@@ -515,6 +519,8 @@ struct dcn_mi_registers {
        type SDPIF_AGP_TOP;\
        type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
        type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
+       type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
+       type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
        type DCHUBBUB_ARB_SAT_LEVEL;\
        type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
        /* todo:  get these from GVM instead of reading registers ourselves */\