clock-div = <1>;
        };
 
+       rng_fck: rng_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
        ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
 
        DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
        DT_CLK(NULL, "sha0_fck", "sha0_fck"),
        DT_CLK(NULL, "aes0_fck", "aes0_fck"),
+       DT_CLK(NULL, "rng_fck", "rng_fck"),
        DT_CLK(NULL, "timer1_fck", "timer1_fck"),
        DT_CLK(NULL, "timer2_fck", "timer2_fck"),
        DT_CLK(NULL, "timer3_fck", "timer3_fck"),