DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d\n",
DRMID(phys_enc->parent),
dpu_encoder_helper_get_intf_type(phys_enc->intf_mode),
- phys_enc->intf_idx - INTF_0, phys_enc->wb_idx - WB_0,
+ phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1,
+ phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1,
phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc,
*/
trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event,
dpu_encoder_helper_get_intf_type(ready_phys->intf_mode),
- ready_phys->intf_idx, ready_phys->wb_idx);
+ ready_phys->hw_intf ? ready_phys->hw_intf->idx : -1,
+ ready_phys->hw_wb ? ready_phys->hw_wb->idx : -1);
return;
}
trace_dpu_enc_trigger_flush(DRMID(drm_enc),
dpu_encoder_helper_get_intf_type(phys->intf_mode),
- phys->intf_idx, phys->wb_idx,
+ phys->hw_intf ? phys->hw_intf->idx : -1,
+ phys->hw_wb ? phys->hw_wb->idx : -1,
pending_kickoff_cnt, ctl->idx,
extra_flush_bits, ret);
}
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
seq_printf(s, "intf:%d wb:%d vsync:%8d underrun:%8d ",
- phys->intf_idx - INTF_0, phys->wb_idx - WB_0,
+ phys->hw_intf ? phys->hw_intf->idx - INTF_0 : -1,
+ phys->hw_wb ? phys->hw_wb->idx - WB_0 : -1,
atomic_read(&phys->vsync_cnt),
atomic_read(&phys->underrun_cnt));
* h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
*/
u32 controller_id = disp_info->h_tile_instance[i];
+ enum dpu_intf intf_idx;
+ enum dpu_wb wb_idx;
if (disp_info->num_of_h_tiles > 1) {
if (i == 0)
DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
i, controller_id, phys_params.split_role);
- phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
+ intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
disp_info->intf_type,
controller_id);
- phys_params.wb_idx = dpu_encoder_get_wb(dpu_kms->catalog,
+ wb_idx = dpu_encoder_get_wb(dpu_kms->catalog,
disp_info->intf_type, controller_id);
- /*
- * The phys_params might represent either an INTF or a WB unit, but not
- * both of them at the same time.
- */
- if ((phys_params.intf_idx == INTF_MAX) &&
- (phys_params.wb_idx == WB_MAX)) {
- DPU_ERROR_ENC(dpu_enc, "could not get intf or wb: type %d, id %d\n",
- disp_info->intf_type, controller_id);
- ret = -EINVAL;
- }
- if ((phys_params.intf_idx != INTF_MAX) &&
- (phys_params.wb_idx != WB_MAX)) {
- DPU_ERROR_ENC(dpu_enc, "both intf and wb present: type %d, id %d\n",
- disp_info->intf_type, controller_id);
- ret = -EINVAL;
- }
+ if (intf_idx >= INTF_0 && intf_idx < INTF_MAX)
+ phys_params.hw_intf = dpu_rm_get_intf(&dpu_kms->rm, intf_idx);
- if (!ret) {
- ret = dpu_encoder_virt_add_phys_encs(disp_info,
- dpu_enc, &phys_params);
- if (ret)
- DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
- }
- }
+ if (wb_idx >= WB_0 && wb_idx < WB_MAX)
+ phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, wb_idx);
- for (i = 0; i < dpu_enc->num_phys_encs; i++) {
- struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
-
- if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)
- phys->hw_intf = dpu_rm_get_intf(&dpu_kms->rm, phys->intf_idx);
-
- if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX)
- phys->hw_wb = dpu_rm_get_wb(&dpu_kms->rm, phys->wb_idx);
-
- if (!phys->hw_intf && !phys->hw_wb) {
+ if (!phys_params.hw_intf && !phys_params.hw_wb) {
DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i);
ret = -EINVAL;
+ break;
}
- if (phys->hw_intf && phys->hw_wb) {
+ if (phys_params.hw_intf && phys_params.hw_wb) {
DPU_ERROR_ENC(dpu_enc,
"invalid phys both intf and wb block at idx: %d\n", i);
ret = -EINVAL;
+ break;
}
+
+ ret = dpu_encoder_virt_add_phys_encs(disp_info,
+ dpu_enc, &phys_params);
+ if (ret) {
+ DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
+ break;
+ }
+
}
mutex_unlock(&dpu_enc->enc_lock);
int i;
phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
- phys_enc->intf_idx = p->intf_idx;
- phys_enc->wb_idx = p->wb_idx;
+ phys_enc->hw_intf = p->hw_intf;
+ phys_enc->hw_wb = p->hw_wb;
phys_enc->parent = p->parent;
phys_enc->dpu_kms = p->dpu_kms;
phys_enc->split_role = p->split_role;
* @enabled: Whether the encoder has enabled and running a mode
* @split_role: Role to play in a split-panel configuration
* @intf_mode: Interface mode
- * @intf_idx: Interface index on dpu hardware
- * @wb_idx: Writeback index on dpu hardware
* @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
* @enable_state: Enable state tracking
* @vblank_refcount: Reference count of vblank request
struct drm_display_mode cached_mode;
enum dpu_enc_split_role split_role;
enum dpu_intf_mode intf_mode;
- enum dpu_intf intf_idx;
- enum dpu_wb wb_idx;
spinlock_t *enc_spinlock;
enum dpu_enc_enable_state enable_state;
atomic_t vblank_refcount;
* @parent: Pointer to the containing virtual encoder
* @parent_ops: Callbacks exposed by the parent to the phys_enc
* @split_role: Role to play in a split-panel configuration
- * @intf_idx: Interface index this phys_enc will control
- * @wb_idx: Writeback index this phys_enc will control
+ * @hw_intf: Hardware interface to the intf registers
+ * @hw_wb: Hardware interface to the wb registers
* @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
*/
struct dpu_enc_phys_init_params {
struct dpu_kms *dpu_kms;
struct drm_encoder *parent;
enum dpu_enc_split_role split_role;
- enum dpu_intf intf_idx;
- enum dpu_wb wb_idx;
+ struct dpu_hw_intf *hw_intf;
+ struct dpu_hw_wb *hw_wb;
spinlock_t *enc_spinlock;
};
#define DPU_DEBUG_CMDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
(e) && (e)->base.parent ? \
(e)->base.parent->base.id : -1, \
- (e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__)
+ (e) ? (e)->base.hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
#define DPU_ERROR_CMDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \
(e) && (e)->base.parent ? \
(e)->base.parent->base.id : -1, \
- (e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__)
+ (e) ? (e)->base.hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
#define to_dpu_encoder_phys_cmd(x) \
container_of(x, struct dpu_encoder_phys_cmd, base)
if (!ctl->ops.setup_intf_cfg)
return;
- intf_cfg.intf = phys_enc->intf_idx;
+ intf_cfg.intf = phys_enc->hw_intf->idx;
intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD;
intf_cfg.stream_sel = cmd_enc->stream_sel;
intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
return;
}
- dpu_encoder_helper_split_config(phys_enc, phys_enc->intf_idx);
+ dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx);
_dpu_encoder_phys_cmd_pingpong_config(phys_enc);
return;
ctl = phys_enc->hw_ctl;
- ctl->ops.update_pending_flush_intf(ctl, phys_enc->intf_idx);
+ ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
}
static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc)
phys_enc->hw_pp->idx);
ctl = phys_enc->hw_ctl;
- ctl->ops.update_pending_flush_intf(ctl, phys_enc->intf_idx);
+ ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
}
phys_enc->enable_state = DPU_ENC_DISABLED;
if (rc) {
DRM_ERROR("failed wait_for_idle: id:%u ret:%d intf:%d\n",
DRMID(phys_enc->parent), rc,
- phys_enc->intf_idx - INTF_0);
+ phys_enc->hw_intf->idx - INTF_0);
}
return rc;
struct dpu_encoder_phys_cmd *cmd_enc = NULL;
int ret = 0;
- DPU_DEBUG("intf %d\n", p->intf_idx - INTF_0);
+ DPU_DEBUG("intf\n");
cmd_enc = kzalloc(sizeof(*cmd_enc), GFP_KERNEL);
if (!cmd_enc) {
cmd_enc->stream_sel = 0;
phys_enc->has_intf_te = test_bit(DPU_INTF_TE,
- &phys_enc->dpu_kms->catalog->intf[p->intf_idx - INTF_0].features);
+ &phys_enc->hw_intf->cap->features);
atomic_set(&cmd_enc->pending_vblank_cnt, 0);
init_waitqueue_head(&cmd_enc->pending_vblank_wq);
projects / nvme.git / commitdiff