u8 reserved[15];
 };
 
+struct ice_aqc_link_topo_addr {
+       u8 lport_num;
+       u8 lport_num_valid;
+#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID       BIT(0)
+       u8 node_type_ctx;
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_S          0
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_M  (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY                0
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL  1
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL   2
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL   3
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED                4
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL    5
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE       6
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ       7
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM  8
+#define ICE_AQC_LINK_TOPO_NODE_CTX_S           4
+#define ICE_AQC_LINK_TOPO_NODE_CTX_M           \
+                               (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
+#define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL      0
+#define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD       1
+#define ICE_AQC_LINK_TOPO_NODE_CTX_PORT                2
+#define ICE_AQC_LINK_TOPO_NODE_CTX_NODE                3
+#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED    4
+#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE    5
+       u8 index;
+       __le16 handle;
+#define ICE_AQC_LINK_TOPO_HANDLE_S     0
+#define ICE_AQC_LINK_TOPO_HANDLE_M     (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
+/* Used to decode the handle field */
+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M    BIT(9)
+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM  BIT(9)
+#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
+#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S                0
+/* In case of a Mezzanine type */
+#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M   \
+                               (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
+#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S        6
+#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M        (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
+/* In case of a LOM type */
+#define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M    \
+                               (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
+};
+
+/* Get Link Topology Handle (direct, 0x06E0) */
+struct ice_aqc_get_link_topo {
+       struct ice_aqc_link_topo_addr addr;
+       u8 node_part_num;
+       u8 rsvd[9];
+};
+
 /* Set Port Identification LED (direct, 0x06E9) */
 struct ice_aqc_set_port_id_led {
        u8 lport_num;
                struct ice_aqc_set_event_mask set_event_mask;
                struct ice_aqc_get_link_status get_link_status;
                struct ice_aqc_event_lan_overflow lan_overflow;
+               struct ice_aqc_get_link_topo get_link_topo;
        } params;
 };
 
        ice_aqc_opc_get_link_status                     = 0x0607,
        ice_aqc_opc_set_event_mask                      = 0x0613,
        ice_aqc_opc_set_mac_lb                          = 0x0620,
+       ice_aqc_opc_get_link_topo                       = 0x06E0,
        ice_aqc_opc_set_port_id_led                     = 0x06E9,
        ice_aqc_opc_sff_eeprom                          = 0x06EE,
 
 
        return status;
 }
 
+/**
+ * ice_aq_get_link_topo_handle - get link topology node return status
+ * @pi: port information structure
+ * @node_type: requested node type
+ * @cd: pointer to command details structure or NULL
+ *
+ * Get link topology node return status for specified node type (0x06E0)
+ *
+ * Node type cage can be used to determine if cage is present. If AQC
+ * returns error (ENOENT), then no cage present. If no cage present, then
+ * connection type is backplane or BASE-T.
+ */
+static enum ice_status
+ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
+                           struct ice_sq_cd *cd)
+{
+       struct ice_aqc_get_link_topo *cmd;
+       struct ice_aq_desc desc;
+
+       cmd = &desc.params.get_link_topo;
+
+       ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
+
+       cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
+                                  ICE_AQC_LINK_TOPO_NODE_CTX_S);
+
+       /* set node type */
+       cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
+
+       return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
+}
+
+/**
+ * ice_is_media_cage_present
+ * @pi: port information structure
+ *
+ * Returns true if media cage is present, else false. If no cage, then
+ * media type is backplane or BASE-T.
+ */
+static bool ice_is_media_cage_present(struct ice_port_info *pi)
+{
+       /* Node type cage can be used to determine if cage is present. If AQC
+        * returns error (ENOENT), then no cage present. If no cage present then
+        * connection type is backplane or BASE-T.
+        */
+       return !ice_aq_get_link_topo_handle(pi,
+                                           ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
+                                           NULL);
+}
+
 /**
  * ice_get_media_type - Gets media type
  * @pi: port information structure
                case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
                case ICE_PHY_TYPE_LOW_25GBASE_SR:
                case ICE_PHY_TYPE_LOW_25GBASE_LR:
-               case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
                case ICE_PHY_TYPE_LOW_40GBASE_SR4:
                case ICE_PHY_TYPE_LOW_40GBASE_LR4:
                case ICE_PHY_TYPE_LOW_50GBASE_SR2:
                case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
                case ICE_PHY_TYPE_LOW_100GBASE_CP2:
                        return ICE_MEDIA_DA;
+               case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
+               case ICE_PHY_TYPE_LOW_40G_XLAUI:
+               case ICE_PHY_TYPE_LOW_50G_LAUI2:
+               case ICE_PHY_TYPE_LOW_50G_AUI2:
+               case ICE_PHY_TYPE_LOW_50G_AUI1:
+               case ICE_PHY_TYPE_LOW_100G_AUI4:
+               case ICE_PHY_TYPE_LOW_100G_CAUI4:
+                       if (ice_is_media_cage_present(pi))
+                               return ICE_MEDIA_DA;
+                       fallthrough;
                case ICE_PHY_TYPE_LOW_1000BASE_KX:
                case ICE_PHY_TYPE_LOW_2500BASE_KX:
                case ICE_PHY_TYPE_LOW_2500BASE_X:
                }
        } else {
                switch (hw_link_info->phy_type_high) {
+               case ICE_PHY_TYPE_HIGH_100G_AUI2:
+               case ICE_PHY_TYPE_HIGH_100G_CAUI2:
+                       if (ice_is_media_cage_present(pi))
+                               return ICE_MEDIA_DA;
+                       fallthrough;
                case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
                        return ICE_MEDIA_BACKPLANE;
                }