arm64: dts: renesas: r9a09g047: Add OPP table

Add OPP table for RZ/G3E SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241203105005.103927-11-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 4176b9aa6892bc2f8c1bbe7ce3c1b2bc58438011..39a7cfb3095b0cc117cc1211a808a77f3c2afb9a 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -20,6 +20,39 @@
                clock-frequency = <0>;
        };
 
+       /*
+        * The default cluster table is based on the assumption that the PLLCA55 clock
+        * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
+        * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
+        * clocked to 1.8GHz as well). The table below should be overridden in the board
+        * DTS based on the PLLCA55 clock frequency.
+        */
+       cluster0_opp: opp-table-0 {
+               compatible = "operating-points-v2";
+
+               opp-1700000000 {
+                       opp-hz = /bits/ 64 <1700000000>;
+                       opp-microvolt = <900000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-850000000 {
+                       opp-hz = /bits/ 64 <850000000>;
+                       opp-microvolt = <800000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-425000000 {
+                       opp-hz = /bits/ 64 <425000000>;
+                       opp-microvolt = <800000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-212500000 {
+                       opp-hz = /bits/ 64 <212500000>;
+                       opp-microvolt = <800000>;
+                       clock-latency-ns = <300000>;
+                       opp-suspend;
+               };
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -30,6 +63,8 @@
                        device_type = "cpu";
                        next-level-cache = <&L3_CA55>;
                        enable-method = "psci";
+                       clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu1: cpu@100 {
@@ -38,6 +73,8 @@
                        device_type = "cpu";
                        next-level-cache = <&L3_CA55>;
                        enable-method = "psci";
+                       clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu2: cpu@200 {
@@ -46,6 +83,8 @@
                        device_type = "cpu";
                        next-level-cache = <&L3_CA55>;
                        enable-method = "psci";
+                       clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu3: cpu@300 {
@@ -54,6 +93,8 @@
                        device_type = "cpu";
                        next-level-cache = <&L3_CA55>;
                        enable-method = "psci";
+                       clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                L3_CA55: cache-controller-0 {