drm/amdgpu: Get atomicOps info from Host for sriov setup

The AtomicOp Requester Enable bit is reserved in VFs and the PF value applies to all
associated VFs. so guest driver can not directly enable the atomicOps for VF, it
depends on PF to enable it. In current design, amdgpu driver  will get the enabled
atomicOps bits through private pf2vf data

Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 41c6b3aacd37921ab5c392ee84240561fb2624bb..aefa96bcbbab4931a223f5a78a0eeb3e19570109 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3530,17 +3530,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
        DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
        DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
 
-       /* enable PCIE atomic ops */
-       r = pci_enable_atomic_ops_to_root(adev->pdev,
-                                         PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
-                                         PCI_EXP_DEVCAP2_ATOMIC_COMP64);
-       if (r) {
-               adev->have_atomics_support = false;
-               DRM_INFO("PCIE atomic ops is not supported\n");
-       } else {
-               adev->have_atomics_support = true;
-       }
-
        amdgpu_device_get_pcie_info(adev);
 
        if (amdgpu_mcbp)
@@ -3563,6 +3552,19 @@ int amdgpu_device_init(struct amdgpu_device *adev,
        if (r)
                return r;
 
+       /* enable PCIE atomic ops */
+       if (amdgpu_sriov_vf(adev))
+               adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
+                       adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_enabled_flags ==
+                       (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
+       else
+               adev->have_atomics_support =
+                       !pci_enable_atomic_ops_to_root(adev->pdev,
+                                         PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
+                                         PCI_EXP_DEVCAP2_ATOMIC_COMP64);
+       if (!adev->have_atomics_support)
+               dev_info(adev->dev, "PCIE atomic ops is not supported\n");
+
        /* doorbell bar mapping and doorbell index init*/
        amdgpu_device_doorbell_init(adev);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
index a434c71fde8ec52476a70f8f2b4d7c7e94c1ef69..995899191288d50bbd30c14e5d7d5e5859d78b98 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
@@ -204,8 +204,10 @@ struct amd_sriov_msg_pf2vf_info {
        } mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST];
        /* UUID info */
        struct amd_sriov_msg_uuid_info uuid_info;
+       /* pcie atomic Ops info */
+       uint32_t pcie_atomic_ops_enabled_flags;
        /* reserved */
-       uint32_t reserved[256 - 47];
+       uint32_t reserved[256 - 48];
 };
 
 struct amd_sriov_msg_vf2pf_info_header {