bool                            debug_enable_ras_aca;
        bool                            debug_exp_resets;
        bool                            debug_disable_gpu_ring_reset;
+       bool                            debug_vm_userptr;
 
        /* Protection for the following isolation structure */
        struct mutex                    enforce_isolation_mutex;
 
        AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5),
        AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6),
        AMDGPU_DEBUG_SMU_POOL = BIT(7),
+       AMDGPU_DEBUG_VM_USERPTR = BIT(8),
 };
 
 unsigned int amdgpu_vram_limit = UINT_MAX;
                pr_info("debug: use vram for smu pool\n");
                adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM;
        }
+       if (amdgpu_debug_mask & AMDGPU_DEBUG_VM_USERPTR) {
+               pr_info("debug: VM mode debug for userptr is enabled\n");
+               adev->debug_vm_userptr = true;
+       }
 }
 
 static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)