* 1078 errata workaround for the 36GB limitation
                 */
                if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078 &&
-                   ioc->dma_mask > DMA_35BIT_MASK) {
+                   ioc->dma_mask > DMA_BIT_MASK(35)) {
                        if (!pci_set_dma_mask(ioc->pcidev, DMA_BIT_MASK(32))
                            && !pci_set_consistent_dma_mask(ioc->pcidev,
                            DMA_BIT_MASK(32))) {
-                               dma_mask = DMA_35BIT_MASK;
+                               dma_mask = DMA_BIT_MASK(35);
                                d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
                                    "setting 35 bit addressing for "
                                    "Request/Reply/Chain and Sense Buffers\n",
                alloc_dma += ioc->reply_sz;
        }
 
-       if (dma_mask == DMA_35BIT_MASK && !pci_set_dma_mask(ioc->pcidev,
+       if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev,
            ioc->dma_mask) && !pci_set_consistent_dma_mask(ioc->pcidev,
            ioc->dma_mask))
                d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
                ioc->sense_buf_pool = NULL;
        }
 
-       if (dma_mask == DMA_35BIT_MASK && !pci_set_dma_mask(ioc->pcidev,
+       if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev,
            DMA_BIT_MASK(64)) && !pci_set_consistent_dma_mask(ioc->pcidev,
            DMA_BIT_MASK(64)))
                d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
 
        /* Setup the HW Tx Head and Tail descriptor pointers */
        ew32(TDLEN(0), tx_ring->count * sizeof(union e1000_adv_tx_desc));
        tdba = tx_ring->dma;
-       ew32(TDBAL(0), (tdba & DMA_32BIT_MASK));
+       ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
        ew32(TDBAH(0), (tdba >> 32));
        ew32(TDH(0), 0);
        ew32(TDT(0), 0);
         * the Base and Length of the Rx Descriptor Ring
         */
        rdba = rx_ring->dma;
-       ew32(RDBAL(0), (rdba & DMA_32BIT_MASK));
+       ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
        ew32(RDBAH(0), (rdba >> 32));
        ew32(RDLEN(0), rx_ring->count * sizeof(union e1000_adv_rx_desc));
        rx_ring->head = E1000_RDH(0);
                return err;
 
        pci_using_dac = 0;
-       err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
+       err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
        if (!err) {
-               err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
+               err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
                if (!err)
                        pci_using_dac = 1;
        } else {
-               err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
+               err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
                if (err) {
-                       err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
+                       err = pci_set_consistent_dma_mask(pdev,
+                                                         DMA_BIT_MASK(32));
                        if (err) {
                                dev_err(&pdev->dev, "No usable DMA "
                                        "configuration, aborting\n");
 
        /* program DMA context */
        hw = &adapter->hw;
        spin_lock_bh(&fcoe->lock);
-       IXGBE_WRITE_REG(hw, IXGBE_FCPTRL, ddp->udp & DMA_32BIT_MASK);
+       IXGBE_WRITE_REG(hw, IXGBE_FCPTRL, ddp->udp & DMA_BIT_MASK(32));
        IXGBE_WRITE_REG(hw, IXGBE_FCPTRH, (u64)ddp->udp >> 32);
        IXGBE_WRITE_REG(hw, IXGBE_FCBUFF, fcbuff);
        IXGBE_WRITE_REG(hw, IXGBE_FCDMARW, fcdmarw);
 
        pci_set_master(pci);
 
        /* check if we can restrict PCI DMA transfers to 32 bits */
-       err = pci_set_dma_mask(pci, DMA_32BIT_MASK);
+       err = pci_set_dma_mask(pci, DMA_BIT_MASK(32));
        if (err < 0) {
                snd_printk(KERN_ERR "architecture does not support "
                           "32bit PCI busmaster DMA\n");