]> www.infradead.org Git - users/hch/configfs.git/commitdiff
i2c: designware: do not hold SCL low when I2C_DYNAMIC_TAR_UPDATE is not set
authorLiu Peibao <loven.liu@jaguarmicro.com>
Fri, 1 Nov 2024 08:12:43 +0000 (16:12 +0800)
committerAndi Shyti <andi.shyti@kernel.org>
Fri, 8 Nov 2024 18:13:06 +0000 (19:13 +0100)
When the Tx FIFO is empty and the last command has no STOP bit
set, the master holds SCL low. If I2C_DYNAMIC_TAR_UPDATE is not
set, BIT(13) MST_ON_HOLD of IC_RAW_INTR_STAT is not enabled,
causing the __i2c_dw_disable() timeout. This is quite similar to
commit 2409205acd3c ("i2c: designware: fix __i2c_dw_disable() in
case master is holding SCL low"). Also check BIT(7)
MST_HOLD_TX_FIFO_EMPTY in IC_STATUS, which is available when
IC_STAT_FOR_CLK_STRETCH is set.

Fixes: 2409205acd3c ("i2c: designware: fix __i2c_dw_disable() in case master is holding SCL low")
Co-developed-by: Xiaowu Ding <xiaowu.ding@jaguarmicro.com>
Signed-off-by: Xiaowu Ding <xiaowu.ding@jaguarmicro.com>
Co-developed-by: Angus Chen <angus.chen@jaguarmicro.com>
Signed-off-by: Angus Chen <angus.chen@jaguarmicro.com>
Signed-off-by: Liu Peibao <loven.liu@jaguarmicro.com>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
drivers/i2c/busses/i2c-designware-common.c
drivers/i2c/busses/i2c-designware-core.h

index f31d352d98b57410f42db51f5ec95e02840f33e0..9d88b4fa03e4235327d96f8ce4da1588715833d2 100644 (file)
@@ -524,7 +524,7 @@ err_release_lock:
 void __i2c_dw_disable(struct dw_i2c_dev *dev)
 {
        struct i2c_timings *t = &dev->timings;
-       unsigned int raw_intr_stats;
+       unsigned int raw_intr_stats, ic_stats;
        unsigned int enable;
        int timeout = 100;
        bool abort_needed;
@@ -532,9 +532,11 @@ void __i2c_dw_disable(struct dw_i2c_dev *dev)
        int ret;
 
        regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &raw_intr_stats);
+       regmap_read(dev->map, DW_IC_STATUS, &ic_stats);
        regmap_read(dev->map, DW_IC_ENABLE, &enable);
 
-       abort_needed = raw_intr_stats & DW_IC_INTR_MST_ON_HOLD;
+       abort_needed = (raw_intr_stats & DW_IC_INTR_MST_ON_HOLD) ||
+                       (ic_stats & DW_IC_STATUS_MASTER_HOLD_TX_FIFO_EMPTY);
        if (abort_needed) {
                if (!(enable & DW_IC_ENABLE_ENABLE)) {
                        regmap_write(dev->map, DW_IC_ENABLE, DW_IC_ENABLE_ENABLE);
index 8e8854ec988258ece4378a872ca0b3beb6fbac94..2d32896d067346a3deced868b062fcede1933d9c 100644 (file)
 #define DW_IC_STATUS_RFNE                      BIT(3)
 #define DW_IC_STATUS_MASTER_ACTIVITY           BIT(5)
 #define DW_IC_STATUS_SLAVE_ACTIVITY            BIT(6)
+#define DW_IC_STATUS_MASTER_HOLD_TX_FIFO_EMPTY BIT(7)
 
 #define DW_IC_SDA_HOLD_RX_SHIFT                        16
 #define DW_IC_SDA_HOLD_RX_MASK                 GENMASK(23, 16)