drm/amdgpu: handle gfx12 in amdgpu_display_verify_sizes

It verified GFX9-11 swizzle modes on GFX12, which has undefined behavior.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index b69a4e1b864b11d8c7a87a10099a0571accd5119..3bb4ca9b8a404d1abf4455ecb97583a291bfb49f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -1082,6 +1082,30 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
                        block_width = 256 / format_info->cpp[i];
                        block_height = 1;
                        block_size_log2 = 8;
+               } else if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX12) {
+                       int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
+
+                       switch (swizzle) {
+                       case AMD_FMT_MOD_TILE_GFX12_256B_2D:
+                               block_size_log2 = 8;
+                               break;
+                       case AMD_FMT_MOD_TILE_GFX12_4K_2D:
+                               block_size_log2 = 12;
+                               break;
+                       case AMD_FMT_MOD_TILE_GFX12_64K_2D:
+                               block_size_log2 = 16;
+                               break;
+                       case AMD_FMT_MOD_TILE_GFX12_256K_2D:
+                               block_size_log2 = 18;
+                               break;
+                       default:
+                               drm_dbg_kms(rfb->base.dev,
+                                           "Gfx12 swizzle mode with unknown block size: %d\n", swizzle);
+                               return -EINVAL;
+                       }
+
+                       get_block_dimensions(block_size_log2, format_info->cpp[i],
+                                            &block_width, &block_height);
                } else {
                        int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
 
@@ -1117,7 +1141,8 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
                        return ret;
        }
 
-       if (AMD_FMT_MOD_GET(DCC, modifier)) {
+       if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) <= AMD_FMT_MOD_TILE_VER_GFX11 &&
+           AMD_FMT_MOD_GET(DCC, modifier)) {
                if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
                        block_size_log2 = get_dcc_block_size(modifier, false, false);
                        get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 4168445fbb8b57cdd94d7844ccec66bd3b25f844..2d84a8052b157cc68e40f40945c13b7d2596c38a 100644 (file)
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -1506,6 +1506,8 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
  *    6 - 64KB_3D
  *    7 - 256KB_3D
  */
+#define AMD_FMT_MOD_TILE_GFX12_256B_2D 1
+#define AMD_FMT_MOD_TILE_GFX12_4K_2D 2
 #define AMD_FMT_MOD_TILE_GFX12_64K_2D 3
 #define AMD_FMT_MOD_TILE_GFX12_256K_2D 4