Merge branch 'for-next/fpsimd' into for-next/core

* for-next/fpsimd:
  arm64: cpufeature: Warn if we attempt to read a zero width field
  arm64: cpufeature: Add missing .field_width for GIC system registers
  arm64: signal: nofpsimd: Do not allocate fp/simd context when not available
  arm64: cpufeature: Always specify and use a field width for capabilities
  arm64: Always use individual bits in CPACR floating point enables
  arm64: Define CPACR_EL1_FPEN similarly to other floating point controls

diff --cc arch/arm64/include/asm/cpufeature.h
Simple merge

diff --cc arch/arm64/include/asm/sysreg.h
index 89b58b73a8c17e98d5936c84073794c84f55b132,e66dd9ebc3374674eff32a969cc2472e4b14632b..2023a0e6c6d6066a79db84fffbe91fd84e29a370
--- 1/arch/arm64/include/asm/sysreg.h
--- 2/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@@ -1109,10 -1097,16 +1109,12 @@@
  #define ZCR_ELx_LEN_SIZE      9
  #define ZCR_ELx_LEN_MASK      0x1ff
  
+ #define CPACR_EL1_FPEN_EL1EN  (BIT(20)) /* enable EL1 access */
+ #define CPACR_EL1_FPEN_EL0EN  (BIT(21)) /* enable EL0 access, if EL1EN set */
+ 
  #define CPACR_EL1_ZEN_EL1EN   (BIT(16)) /* enable EL1 access */
  #define CPACR_EL1_ZEN_EL0EN   (BIT(17)) /* enable EL0 access, if EL1EN set */
- #define CPACR_EL1_ZEN         (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
  
 -/* TCR EL1 Bit Definitions */
 -#define SYS_TCR_EL1_TCMA1     (BIT(58))
 -#define SYS_TCR_EL1_TCMA0     (BIT(57))
 -
  /* GCR_EL1 Definitions */
  #define SYS_GCR_EL1_RRND      (BIT(16))
  #define SYS_GCR_EL1_EXCL_MASK 0xffffUL

diff --cc arch/arm64/kernel/cpufeature.c
index 074905ac844491f97de821dbffc29b266bd3bcab,499e37a301568b81e3730d23652ece7a804e93b5..32aa0eb3ed688b7421bb01030274bf1919c35039
--- 1/arch/arm64/kernel/cpufeature.c
--- 2/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@@ -2147,8 -2157,10 +2162,9 @@@ static const struct arm64_cpu_capabilit
                .sys_reg = SYS_ID_AA64MMFR2_EL1,
                .sign = FTR_UNSIGNED,
                .field_pos = ID_AA64MMFR2_FWB_SHIFT,
+               .field_width = 4,
                .min_field_value = 1,
                .matches = has_cpuid_feature,
 -              .cpu_enable = cpu_has_fwb,
        },
        {
                .desc = "ARMv8.4 Translation Table Level",
@@@ -2243,16 -2263,6 +2267,17 @@@
                .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
                .matches = has_address_auth_cpucap,
        },
 +      {
 +              .desc = "Address authentication (architected QARMA3 algorithm)",
 +              .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3,
 +              .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
 +              .sys_reg = SYS_ID_AA64ISAR2_EL1,
 +              .sign = FTR_UNSIGNED,
 +              .field_pos = ID_AA64ISAR2_APA3_SHIFT,
++              .field_width = 4,
 +              .min_field_value = ID_AA64ISAR2_APA3_ARCHITECTED,
 +              .matches = has_address_auth_cpucap,
 +      },
        {
                .desc = "Address authentication (IMP DEF algorithm)",
                .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
@@@ -2278,16 -2290,6 +2305,17 @@@
                .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
                .matches = has_cpuid_feature,
        },
 +      {
 +              .desc = "Generic authentication (architected QARMA3 algorithm)",
 +              .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3,
 +              .type = ARM64_CPUCAP_SYSTEM_FEATURE,
 +              .sys_reg = SYS_ID_AA64ISAR2_EL1,
 +              .sign = FTR_UNSIGNED,
 +              .field_pos = ID_AA64ISAR2_GPA3_SHIFT,
++              .field_width = 4,
 +              .min_field_value = ID_AA64ISAR2_GPA3_ARCHITECTED,
 +              .matches = has_cpuid_feature,
 +      },
        {
                .desc = "Generic authentication (IMP DEF algorithm)",
                .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
@@@ -2433,15 -2444,12 +2470,16 @@@
  static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
        {
                HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
-                                 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
+                                 4, FTR_UNSIGNED,
+                                 ID_AA64ISAR1_APA_ARCHITECTED)
        },
-                                 FTR_UNSIGNED, ID_AA64ISAR2_APA3_ARCHITECTED)
 +      {
 +              HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT,
++                                4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_ARCHITECTED)
 +      },
        {
                HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
-                                 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
+                                 4, FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
        },
        {},
  };
@@@ -2449,15 -2457,11 +2487,15 @@@
  static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
        {
                HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
-                                 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
+                                 4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
        },
-                                 FTR_UNSIGNED, ID_AA64ISAR2_GPA3_ARCHITECTED)
 +      {
 +              HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT,
++                                4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_ARCHITECTED)
 +      },
        {
                HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
-                                 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
+                                 4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
        },
        {},
  };
@@@ -2519,12 -2523,11 +2557,12 @@@ static const struct arm64_cpu_capabilit
        HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
  #endif
  #ifdef CONFIG_ARM64_MTE
-       HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
-       HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3),
+       HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
++      HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3),
  #endif /* CONFIG_ARM64_MTE */
-       HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
-       HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
-       HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
+       HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
+       HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
+       HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
        {},
  };
  

diff --cc arch/arm64/kernel/signal.c
Simple merge