spin_lock_bh(&hw->cmq.csq.lock);
 
-       if (num > hclge_ring_space(&hw->cmq.csq)) {
+       if (num > hclge_ring_space(&hw->cmq.csq) ||
+           test_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state)) {
                spin_unlock_bh(&hw->cmq.csq.lock);
                return -EBUSY;
        }
        spin_lock_init(&hdev->hw.cmq.crq.lock);
 
        hclge_cmd_init_regs(&hdev->hw);
+       clear_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
 
        ret = hclge_cmd_query_firmware_version(&hdev->hw, &version);
        if (ret) {
 
 
        /* check for vector0 reset event sources */
        if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
+               set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
                set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
                *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
                return HCLGE_VECTOR0_EVENT_RST;
        }
 
        if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
+               set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
                set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
                *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
                return HCLGE_VECTOR0_EVENT_RST;
 
        HCLGE_STATE_MBX_SERVICE_SCHED,
        HCLGE_STATE_MBX_HANDLING,
        HCLGE_STATE_STATISTICS_UPDATING,
+       HCLGE_STATE_CMD_DISABLE,
        HCLGE_STATE_MAX
 };