Merge branches 'msm-next-lumag-core', 'msm-next-lumag-dpu', 'msm-next-lumag-dp',...

Core:
- MSM_INFO_GET_FLAGS support
- Cleaned up MSM IOMMU wrapper code

DPU:
- Added support for XR30 and P010 image formats
- Reworked MDSS/DPU schema, added SM8250 MDSS bindings
- Added Qualcomm SM6115 support

DP:
- Dropped unsane sanity checks

DSI:
- Fix calculation of DSC pps payload

DSI PHY:
- DSI PHY support for QCM2290

HDMI:
- Reworked dev init path

And, as usual, small misc fixes.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --cc drivers/gpu/drm/msm/msm_mdss.c
index 6a4549ef34d408fb69f2a8117bdb6eb2d85f038b,4b60637916c1d8cf0ed5653fd2bd5fb549f62024,e13c5c12b775fabd13fbe55d5a390f0c74d00e57,e13c5c12b775fabd13fbe55d5a390f0c74d00e57,e13c5c12b775fabd13fbe55d5a390f0c74d00e57,e13c5c12b775fabd13fbe55d5a390f0c74d00e57..86b28add1ffff4f32eba624b34a761479fe87811
--- 1/drivers/gpu/drm/msm/msm_mdss.c
--- 2/drivers/gpu/drm/msm/msm_mdss.c
--- 3/drivers/gpu/drm/msm/msm_mdss.c
--- 4/drivers/gpu/drm/msm/msm_mdss.c
--- 5/drivers/gpu/drm/msm/msm_mdss.c
--- 6/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@@@@@@ -261,27 -201,27 -201,23 -201,23 -201,23 -201,23 +261,31 @@@@@@@ static int msm_mdss_enable(struct msm_m
        /*
         * ubwc config is part of the "mdss" region which is not accessible
         * from the rest of the driver. hardcode known configurations here
 +++++   *
 +++++   * Decoder version can be read from the UBWC_DEC_HW_VERSION reg,
 +++++   * UBWC_n and the rest of params comes from hw_catalog.
 +++++   * Unforunately this driver can not access hw catalog, so we have to
 +++++   * hardcode them here.
         */
 -----  switch (readl_relaxed(msm_mdss->mmio + HW_REV)) {
 +++++  switch (hw_rev) {
        case DPU_HW_VER_500:
        case DPU_HW_VER_501:
 -----          writel_relaxed(0x420, msm_mdss->mmio + UBWC_STATIC);
 +++++          msm_mdss_setup_ubwc_dec_30(msm_mdss, UBWC_3_0, 0, 2, 0);
                break;
        case DPU_HW_VER_600:
 -----          /* TODO: 0x102e for LP_DDR4 */
 -----          writel_relaxed(0x103e, msm_mdss->mmio + UBWC_STATIC);
 -----          writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
 -----          writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);
 +++++          /* TODO: highest_bank_bit = 2 for LP_DDR4 */
 +++++          msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
                break;
        case DPU_HW_VER_620:
 -----          writel_relaxed(0x1e, msm_mdss->mmio + UBWC_STATIC);
 +++++          /* UBWC_2_0 */
 +++++          msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
  ++++          break;
+ ++++  case DPU_HW_VER_630:
+ ++++          /* UBWC_2_0 */
+ ++++          msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x11f);
+               break;
        case DPU_HW_VER_720:
 -----          writel_relaxed(0x101e, msm_mdss->mmio + UBWC_STATIC);
 +++++          msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
                break;
        }