phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoC

UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init
sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance
reusing the G4 init sequence of SM8350.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-12-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index b784eed2eb1fe4d53080a7459fb2eda00fe48245..5cdac38c5fdc137dc49c56bd6b266e289cead896 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -942,6 +942,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
                .serdes         = sm8350_ufsphy_hs_b_serdes,
                .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
        },
+       .tbls_hs_g4 = {
+               .tx             = sm8350_ufsphy_g4_tx,
+               .tx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
+               .rx             = sm8350_ufsphy_g4_rx,
+               .rx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
+               .pcs            = sm8350_ufsphy_g4_pcs,
+               .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+       },
        .clk_list               = sm8450_ufs_phy_clk_l,
        .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
        .vreg_list              = qmp_phy_vreg_l,