drm/amdgpu: Enable CP idle interrupts

v1: The interrupts need to be enabled to move to DS clocks.
v2: Don't enable GFX IDLE interrupts if there are no GFX rings.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 82c7d04f4aed58dc4a54656e4c262931ffc4e208..7cd07765e9d95e83cc7a80db690462dd4ffe7c52 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2669,17 +2669,15 @@ static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
 {
        u32 tmp;
 
-       /* don't toggle interrupts that are only applicable
-        * to me0 pipe0 on AISCs that have me0 removed */
-       if (!adev->gfx.num_gfx_rings)
-               return;
+       /* These interrupts should be enabled to drive DS clock */
 
        tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
 
        tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
        tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
        tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
-       tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
+       if(adev->gfx.num_gfx_rings)
+               tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
 
        WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
 }