drm/amd/display: determine USB C DP2 mode only when USB DP Alt is enabled

[why]
When display is connected with a native DP port, DP2 mode register value
is a don't care. Driver mistakenly reduce max supported lane count to 2
lane based on the don't care value.

[how]
Add additional check only if USB C DP alt mode is enabled, we will
determine max lane count supported based on current mode.

Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index b66d416ed1675937202e2479b70bb2112adafb21..6e99b8c3b5ffbdb19a36156bd04e5f2bc657dd65 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -682,7 +682,7 @@ static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
                       new_edid->raw_edid, new_edid->length) == 0);
 }
 
-static bool wait_for_alt_mode(struct dc_link *link)
+static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 {
        /**
         * something is terribly wrong if time out is > 200ms. (5Hz)
@@ -836,7 +836,7 @@ static bool dc_link_detect_helper(struct dc_link *link,
                        /* wa HPD high coming too early*/
                        if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
                                /* if alt mode times out, return false */
-                               if (!wait_for_alt_mode(link))
+                               if (!wait_for_entering_dp_alt_mode(link))
                                        return false;
                        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 7cbb1efb4f68eb245c33eb7dd525256a6ea0b9ed..74cf06aacd6c16bc93c1296f240620f0c2cc589b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1710,19 +1710,10 @@ bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
 
 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
 {
-       /* Set Default link settings */
-       struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
-                       LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
-
-       /* Higher link settings based on feature supported */
-       if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
-               max_link_cap.link_rate = LINK_RATE_HIGH2;
-
-       if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
-               max_link_cap.link_rate = LINK_RATE_HIGH3;
+       struct dc_link_settings max_link_cap = {0};
 
-       if (link->link_enc->funcs->get_max_link_cap)
-               link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
+       /* get max link encoder capability */
+       link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
 
        /* Lower link settings based on sink's link cap */
        if (link->reported_link_cap.lane_count < max_link_cap.lane_count)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 8527cce81c6fb8f315d7d88f7cfa2ea0fa43bc5a..8d8c84c81b34e2105c0a320d9122ed5094beddc5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -118,7 +118,8 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = {
        .enable_hpd = dce110_link_encoder_enable_hpd,
        .disable_hpd = dce110_link_encoder_disable_hpd,
        .is_dig_enabled = dce110_is_dig_enabled,
-       .destroy = dce110_link_encoder_destroy
+       .destroy = dce110_link_encoder_destroy,
+       .get_max_link_cap = dce110_link_encoder_get_max_link_cap
 };
 
 static enum bp_result link_transmitter_control(
@@ -1389,3 +1390,20 @@ void dce110_link_encoder_disable_hpd(struct link_encoder *enc)
 
        set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN);
 }
+
+void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc,
+       struct dc_link_settings *link_settings)
+{
+       /* Set Default link settings */
+       struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
+                       LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
+
+       /* Higher link settings based on feature supported */
+       if (enc->features.flags.bits.IS_HBR2_CAPABLE)
+               max_link_cap.link_rate = LINK_RATE_HIGH2;
+
+       if (enc->features.flags.bits.IS_HBR3_CAPABLE)
+               max_link_cap.link_rate = LINK_RATE_HIGH3;
+
+       *link_settings = max_link_cap;
+}

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index 3c9368df4093ac0f52177fb8a733f244c1f804d6..384389f0e2c313c1feb9e4e65176989d89266396 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -271,4 +271,7 @@ void dce110_psr_program_secondary_packet(struct link_encoder *enc,
 
 bool dce110_is_dig_enabled(struct link_encoder *enc);
 
+void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc,
+       struct dc_link_settings *link_settings);
+
 #endif /* __DC_LINK_ENCODER__DCE110_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index d3617d6785a7edafa8d28314d67854295e0ca0b9..7fd385be3f3def5756ef9fd88e6e5c66f720cbb4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -90,7 +90,8 @@ static const struct link_encoder_funcs dcn10_lnk_enc_funcs = {
        .is_dig_enabled = dcn10_is_dig_enabled,
        .get_dig_frontend = dcn10_get_dig_frontend,
        .get_dig_mode = dcn10_get_dig_mode,
-       .destroy = dcn10_link_encoder_destroy
+       .destroy = dcn10_link_encoder_destroy,
+       .get_max_link_cap = dcn10_link_encoder_get_max_link_cap,
 };
 
 static enum bp_result link_transmitter_control(
@@ -1370,7 +1371,6 @@ void dcn10_link_encoder_disable_hpd(struct link_encoder *enc)
                        DC_HPD_EN, 0);
 }
 
-
 #define AUX_REG(reg)\
        (enc10->aux_regs->reg)
 
@@ -1425,3 +1425,19 @@ enum signal_type dcn10_get_dig_mode(
        return SIGNAL_TYPE_NONE;
 }
 
+void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
+       struct dc_link_settings *link_settings)
+{
+       /* Set Default link settings */
+       struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
+                       LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
+
+       /* Higher link settings based on feature supported */
+       if (enc->features.flags.bits.IS_HBR2_CAPABLE)
+               max_link_cap.link_rate = LINK_RATE_HIGH2;
+
+       if (enc->features.flags.bits.IS_HBR3_CAPABLE)
+               max_link_cap.link_rate = LINK_RATE_HIGH3;
+
+       *link_settings = max_link_cap;
+}

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index 762109174fb879650a32df771596410d43d2f564..68395bcc24fddf93b1715ce783c6b7b61de72610 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -575,4 +575,7 @@ void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
 
 enum signal_type dcn10_get_dig_mode(
        struct link_encoder *enc);
+
+void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
+       struct dc_link_settings *link_settings);
 #endif /* __DC_LINK_ENCODER__DCN10_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
index 15d513b79667fac800edff0b961bc39f7bdf3279..8d209dae66e6ae8a8130edfd6da07424346d6a19 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
@@ -49,6 +49,12 @@
 #define IND_REG(index) \
        (enc10->link_regs->index)
 
+#ifndef MAX
+#define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
+#endif
+#ifndef MIN
+#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
+#endif
 
 static struct mpll_cfg dcn2_mpll_cfg[] = {
        // RBR
@@ -260,6 +266,38 @@ void dcn20_link_encoder_enable_dp_output(
 
 }
 
+void dcn20_link_encoder_get_max_link_cap(struct link_encoder *enc,
+       struct dc_link_settings *link_settings)
+{
+       struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+       uint32_t is_in_usb_c_dp4_mode = 0;
+
+       dcn10_link_encoder_get_max_link_cap(enc, link_settings);
+
+       /* in usb c dp2 mode, max lane count is 2 */
+       if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
+               REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
+               if (!is_in_usb_c_dp4_mode)
+                       link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
+       }
+
+}
+
+bool dcn20_link_encoder_is_in_alt_mode(struct link_encoder *enc)
+{
+       struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+       uint32_t dp_alt_mode_disable = 0;
+       bool is_usb_c_alt_mode = false;
+
+       if (enc->features.flags.bits.DP_IS_USB_C) {
+               /* if value == 1 alt mode is disabled, otherwise it is enabled */
+               REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
+               is_usb_c_alt_mode = (dp_alt_mode_disable == 0);
+       }
+
+       return is_usb_c_alt_mode;
+}
+
 #define AUX_REG(reg)\
        (enc10->aux_regs->reg)
 
@@ -311,28 +349,6 @@ void enc2_hw_init(struct link_encoder *enc)
        dcn10_aux_initialize(enc10);
 }
 
-void dcn20_link_encoder_get_max_link_cap(struct link_encoder *enc,
-       struct dc_link_settings *link_settings)
-{
-       struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
-       uint32_t value;
-
-       REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &value);
-
-       if (!value && link_settings->lane_count > LANE_COUNT_TWO)
-               link_settings->lane_count = LANE_COUNT_TWO;
-}
-bool dcn20_link_encoder_is_in_alt_mode(struct link_encoder *enc)
-{
-       struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
-       uint32_t value;
-
-       REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &value);
-
-       // if value == 1 alt mode is disabled, otherwise it is enabled
-       return !value;
-}
-
 static const struct link_encoder_funcs dcn20_link_enc_funcs = {
        .read_state = link_enc2_read_state,
        .validate_output_with_stream =

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
index 8cab8107fd94c2094610685a1e2bd6db0f15c027..284a1ee4d249ef1bfe15326bf01766f1d9a2d121 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
@@ -343,6 +343,10 @@ void dcn20_link_encoder_enable_dp_output(
        const struct dc_link_settings *link_settings,
        enum clock_source_id clock_source);
 
+bool dcn20_link_encoder_is_in_alt_mode(struct link_encoder *enc);
+void dcn20_link_encoder_get_max_link_cap(struct link_encoder *enc,
+       struct dc_link_settings *link_settings);
+
 void dcn20_link_encoder_construct(
        struct dcn20_link_encoder *enc20,
        const struct encoder_init_data *init_data,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
index e45683ac871a2ba86d898bab5175ad10393db0cd..aa46c35b05a23b29052c22a85890b56e5f8f3643 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
@@ -203,29 +203,6 @@ static bool update_cfg_data(
        return true;
 }
 
-void dcn21_link_encoder_get_max_link_cap(struct link_encoder *enc,
-       struct dc_link_settings *link_settings)
-{
-       struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
-       uint32_t value;
-
-       REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &value);
-
-       if (!value && link_settings->lane_count > LANE_COUNT_TWO)
-               link_settings->lane_count = LANE_COUNT_TWO;
-}
-
-bool dcn21_link_encoder_is_in_alt_mode(struct link_encoder *enc)
-{
-       struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
-       uint32_t value;
-
-       REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &value);
-
-       // if value == 1 alt mode is disabled, otherwise it is enabled
-       return !value;
-}
-
 bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc)
 {
        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
@@ -348,8 +325,8 @@ static const struct link_encoder_funcs dcn21_link_enc_funcs = {
        .fec_set_ready = enc2_fec_set_ready,
        .fec_is_active = enc2_fec_is_active,
        .get_dig_frontend = dcn10_get_dig_frontend,
-       .is_in_alt_mode = dcn21_link_encoder_is_in_alt_mode,
-       .get_max_link_cap = dcn21_link_encoder_get_max_link_cap,
+       .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
+       .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
 };
 
 void dcn21_link_encoder_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
index 3464b2d5b89afa1d90dec9bb83ead082c1ba9986..348e9a600a728961c14d8ee02d392e63c9f38182 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
@@ -84,6 +84,14 @@ static void virtual_link_encoder_destroy(struct link_encoder **enc)
        *enc = NULL;
 }
 
+static void virtual_link_encoder_get_max_link_cap(struct link_encoder *enc,
+               struct dc_link_settings *link_settings)
+{
+       /* Set Default link settings */
+       struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
+                               LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
+       *link_settings = max_link_cap;
+}
 
 static const struct link_encoder_funcs virtual_lnk_enc_funcs = {
        .validate_output_with_stream =
@@ -94,6 +102,7 @@ static const struct link_encoder_funcs virtual_lnk_enc_funcs = {
        .enable_dp_output = virtual_link_encoder_enable_dp_output,
        .enable_dp_mst_output = virtual_link_encoder_enable_dp_mst_output,
        .disable_output = virtual_link_encoder_disable_output,
+       .get_max_link_cap = virtual_link_encoder_get_max_link_cap,
        .dp_set_lane_settings = virtual_link_encoder_dp_set_lane_settings,
        .dp_set_phy_pattern = virtual_link_encoder_dp_set_phy_pattern,
        .update_mst_stream_allocation_table =