drm/amdgpu/jpeg: skip set pg for sriov

Host handles PG.

Signed-off-by: Vignesh Chander <Vignesh.Chander@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index 1de79d660285d796637a95e4120d8a1d604ef493..355d25fd6169750e0324ef9a712594aaf4dd642f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -360,10 +360,8 @@ static int jpeg_v4_0_3_hw_fini(void *handle)
 
        cancel_delayed_work_sync(&adev->jpeg.idle_work);
 
-       if (!amdgpu_sriov_vf(adev)) {
-               if (adev->jpeg.cur_state != AMD_PG_STATE_GATE)
-                       ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
-       }
+       if (adev->jpeg.cur_state != AMD_PG_STATE_GATE)
+               ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
 
        return ret;
 }
@@ -950,6 +948,11 @@ static int jpeg_v4_0_3_set_powergating_state(void *handle,
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        int ret;
 
+       if (amdgpu_sriov_vf(adev)) {
+               adev->jpeg.cur_state = AMD_PG_STATE_UNGATE;
+               return 0;
+       }
+
        if (state == adev->jpeg.cur_state)
                return 0;
 

diff --git a/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h b/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h
index 796d4f8791e5f5f8727296794d595efe5adb6a4b..ced26cc5123abf6a036046427f391891b2b5f960 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h
@@ -35,13 +35,11 @@
 
 #define MMSCH_VF_ENGINE_STATUS__PASS 0x1
 
-#define MMSCH_VF_MAILBOX_RESP__OK 0x1
-#define MMSCH_VF_MAILBOX_RESP__INCOMPLETE 0x2
-
-#define MMSCH_VF_ENGINE_STATUS__PASS 0x1
-
-#define MMSCH_VF_MAILBOX_RESP__OK 0x1
-#define MMSCH_VF_MAILBOX_RESP__INCOMPLETE 0x2
+#define MMSCH_VF_MAILBOX_RESP__OK                      0x1
+#define MMSCH_VF_MAILBOX_RESP__INCOMPLETE              0x2
+#define MMSCH_VF_MAILBOX_RESP__FAILED                  0x3
+#define MMSCH_VF_MAILBOX_RESP__FAILED_SMALL_CTX_SIZE   0x4
+#define MMSCH_VF_MAILBOX_RESP__UNKNOWN_CMD             0x5
 
 #define MMSCH_V4_0_VCN_INSTANCES 0x2