powerpc/perf: Cleanup cache_sel bits comment

Update the raw event code comment in power9-pmu.c with respect to
"cache" bits, since power9 MMCRC does not support these.

Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c
index e012b1030a5b186ae797cc8516934096b0b45ddb..a5f8c563001b5acb7c84f60feabc18b62c286561 100644 (file)
--- a/arch/powerpc/perf/power9-pmu.c
+++ b/arch/powerpc/perf/power9-pmu.c
@@ -63,16 +63,8 @@
  *     MMCRA[9:11] = thresh_cmp[0:2]
  *     MMCRA[12:18] = thresh_cmp[3:9]
  *
- * if unit == 6 or unit == 7
- *     MMCRC[53:55] = cache_sel[1:3]      (L2EVENT_SEL)
- * else if unit == 8 or unit == 9:
- *     if cache_sel[0] == 0: # L3 bank
- *             MMCRC[47:49] = cache_sel[1:3]  (L3EVENT_SEL0)
- *     else if cache_sel[0] == 1:
- *             MMCRC[50:51] = cache_sel[2:3]  (L3EVENT_SEL1)
- * else if cache_sel[1]: # L1 event
- *     MMCR1[16] = cache_sel[2]
- *    MMCR1[17] = cache_sel[3]
+ * MMCR1[16] = cache_sel[2]
+ * MMCR1[17] = cache_sel[3]
  *
  * if mark:
  *     MMCRA[63]    = 1                (SAMPLE_ENABLE)