ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
value);
- /* (void) */ dpm->finish(dpm);
+ dpm->finish(dpm);
return retval;
}
ARMV5_T_MRRC(cpnum, op, 0, 1, crm),
value);
- /* (void) */ dpm->finish(dpm);
+ dpm->finish(dpm);
return retval;
}
ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
value);
- /* (void) */ dpm->finish(dpm);
+ dpm->finish(dpm);
return retval;
}
retval = dpm->instr_write_data_r0_r1(dpm,
ARMV5_T_MCRR(cpnum, op, 0, 1, crm), value);
- /* (void) */ dpm->finish(dpm);
+ dpm->finish(dpm);
return retval;
}
*/
fail:
- /* (void) */ dpm->finish(dpm);
+ dpm->finish(dpm);
return retval;
}
cache->reg_list[i].dirty = false;
}
- /* (void) */ dpm->finish(dpm);
+ dpm->finish(dpm);
done:
return retval;
}
/* always clean up, regardless of error */
if (mode != ARM_MODE_ANY)
- /* (void) */ arm_dpm_modeswitch(dpm, ARM_MODE_ANY);
+ arm_dpm_modeswitch(dpm, ARM_MODE_ANY);
fail:
- /* (void) */ dpm->finish(dpm);
+ dpm->finish(dpm);
return retval;
}
/* always clean up, regardless of error */
if (mode != ARM_MODE_ANY)
- /* (void) */ arm_dpm_modeswitch(dpm, ARM_MODE_ANY);
+ arm_dpm_modeswitch(dpm, ARM_MODE_ANY);
fail:
- /* (void) */ dpm->finish(dpm);
+ dpm->finish(dpm);
return retval;
}
} while (did_read);
retval = arm_dpm_modeswitch(dpm, ARM_MODE_ANY);
- /* (void) */ dpm->finish(dpm);
+ dpm->finish(dpm);
done:
return retval;
}
ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
value);
- /* (void) */ dpm->finish(dpm);
+ dpm->finish(dpm);
return retval;
}
ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
value);
- /* (void) */ dpm->finish(dpm);
+ dpm->finish(dpm);
return retval;
}
goto fail;
fail:
- /* (void) */ dpm->finish(dpm);
+ dpm->finish(dpm);
return retval;
}
} while (did_read);
retval = armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
- /* (void) */ dpm->finish(dpm);
+ dpm->finish(dpm);
done:
return retval;
}