drm/vc4: hdmi: Do the VID_CTL configuration at once

The VID_CTL setup is done in several places in the driver even though it's
not really required. Let's simplify it a bit to do the configuration in one
go.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://patchwork.freedesktop.org/patch/msgid/08e7ebb605a560fcc149b69b4af52753a7870b2f.1599120059.git-series.maxime@cerno.tech

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 128d33c8c2c3b852576af5d266ddfbff691f246d..8bf69cafdd7e76bbd12a375ecca5bf1c24e064f7 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -428,10 +428,6 @@ static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 
        HDMI_WRITE(HDMI_VERTB0, vertb_even);
        HDMI_WRITE(HDMI_VERTB1, vertb);
-
-       HDMI_WRITE(HDMI_VID_CTL,
-                  (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
-                  (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 }
 
 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
@@ -520,8 +516,6 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder)
        if (vc4_hdmi->variant->phy_init)
                vc4_hdmi->variant->phy_init(vc4_hdmi, mode);
 
-       HDMI_WRITE(HDMI_VID_CTL, 0);
-
        HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
                   HDMI_READ(HDMI_SCHEDULER_CONTROL) |
                   VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
@@ -555,15 +549,19 @@ static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder)
 
 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder)
 {
+       struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
        struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
        struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
+       bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
+       bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
        int ret;
 
        HDMI_WRITE(HDMI_VID_CTL,
-                  HDMI_READ(HDMI_VID_CTL) |
                   VC4_HD_VID_CTL_ENABLE |
                   VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
-                  VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
+                  VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
+                  (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
+                  (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 
        if (vc4_encoder->hdmi_monitor) {
                HDMI_WRITE(HDMI_SCHEDULER_CONTROL,