/* Registers from ACP_INTR block */
 #define ACP3X_EXT_INTR_STAT                    0x1808
 #define ACP5X_EXT_INTR_STAT                    0x1808
+#define ACP6X_EXTERNAL_INTR_ENB                        0x1A00
+#define ACP6X_EXTERNAL_INTR_CNTL               0x1A04
 #define ACP6X_EXT_INTR_STAT                     0x1A0C
+#define ACP6X_EXT_INTR_STAT1                   0x1A10
 
 #define ACP3X_DSP_SW_INTR_BASE                 0x1814
 #define ACP5X_DSP_SW_INTR_BASE                 0x1814
 
 #define ACP_ERROR_IRQ_MASK                     BIT(29)
 #define ACP_SDW0_IRQ_MASK                      BIT(21)
 #define ACP_SDW1_IRQ_MASK                      BIT(2)
+#define SDW_ACPI_ADDR_ACP63                    5
 #define ACP_DEFAULT_SRAM_LENGTH                        0x00080000
 #define ACP_SRAM_PAGE_COUNT                    128
+#define ACP6X_SDW_MAX_MANAGER_COUNT            2
 
 enum clock_source {
        ACP_CLOCK_96M = 0,
 
        .rev            = 6,
        .host_bridge_id = HOST_BRIDGE_ACP63,
        .pgfsm_base     = ACP6X_PGFSM_BASE,
+       .ext_intr_enb = ACP6X_EXTERNAL_INTR_ENB,
+       .ext_intr_cntl = ACP6X_EXTERNAL_INTR_CNTL,
        .ext_intr_stat  = ACP6X_EXT_INTR_STAT,
+       .ext_intr_stat1 = ACP6X_EXT_INTR_STAT1,
        .dsp_intr_base  = ACP6X_DSP_SW_INTR_BASE,
        .sram_pte_offset = ACP6X_SRAM_PTE_OFFSET,
        .hw_semaphore_offset = ACP6X_AXI2DAGB_SEM_0,
        .fusion_dsp_offset = ACP6X_DSP_FUSION_RUNSTALL,
        .probe_reg_offset = ACP6X_FUTURE_REG_ACLK_0,
+       .sdw_max_link_count = ACP6X_SDW_MAX_MANAGER_COUNT,
+       .sdw_acpi_dev_addr = SDW_ACPI_ADDR_ACP63,
+       .reg_start_addr = ACP6x_REG_START,
+       .reg_end_addr = ACP6x_REG_END,
 };
 
 static const struct sof_dev_desc acp63_desc = {