ASoC: msm8916-wcd-analog: fix register Interrupt offset

[ Upstream commit ff69c97ef84c9f7795adb49e9f07c9adcdd0c288 ]

For some reason interrupt set and clear register offsets are
not set correctly.
This patch corrects them!

Fixes: 585e881e5b9e ("ASoC: codecs: Add msm8916-wcd analog codec")
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200811103452.20448-1-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/sound/soc/codecs/msm8916-wcd-analog.c b/sound/soc/codecs/msm8916-wcd-analog.c
index 84289ebeae87251ccdc86b5e6e91b454ceb8fb98..337bddb7c2a49e8f763a37aacebe052e635c3c8d 100644 (file)
--- a/sound/soc/codecs/msm8916-wcd-analog.c
+++ b/sound/soc/codecs/msm8916-wcd-analog.c
@@ -19,8 +19,8 @@
 
 #define CDC_D_REVISION1                        (0xf000)
 #define CDC_D_PERPH_SUBTYPE            (0xf005)
-#define CDC_D_INT_EN_SET               (0x015)
-#define CDC_D_INT_EN_CLR               (0x016)
+#define CDC_D_INT_EN_SET               (0xf015)
+#define CDC_D_INT_EN_CLR               (0xf016)
 #define MBHC_SWITCH_INT                        BIT(7)
 #define MBHC_MIC_ELECTRICAL_INS_REM_DET        BIT(6)
 #define MBHC_BUTTON_PRESS_DET          BIT(5)