adapter->tx_itr_setting = ec->tx_coalesce_usecs;
 
        if (adapter->tx_itr_setting == 1)
-               tx_itr_param = IXGBE_10K_ITR;
+               tx_itr_param = IXGBE_12K_ITR;
        else
                tx_itr_param = adapter->tx_itr_setting;
 
 
 #define IXGBE_MIN_RSC_ITR      24
 #define IXGBE_100K_ITR         40
 #define IXGBE_20K_ITR          200
-#define IXGBE_10K_ITR          400
-#define IXGBE_8K_ITR           500
+#define IXGBE_12K_ITR          336
 
 /* Helper macros to switch between ints/sec and what the register uses.
  * And yes, it's the same math going both ways.  The lowest value
 
                if (q_vector->tx.ring && !q_vector->rx.ring) {
                        /* Tx only vector */
                        if (adapter->tx_itr_setting == 1)
-                               q_vector->itr = IXGBE_10K_ITR;
+                               q_vector->itr = IXGBE_12K_ITR;
                        else
                                q_vector->itr = adapter->tx_itr_setting;
                } else {
        /* simple throttle rate management
         *    0-20MB/s lowest (100000 ints/s)
         *   20-100MB/s low   (20000 ints/s)
-        *  100-1249MB/s bulk (8000 ints/s)
+        *  100-1249MB/s bulk (12000 ints/s)
         */
        /* what was last interrupt timeslice? */
        timepassed_us = q_vector->itr >> 2;
                break;
        case bulk_latency:
        default:
-               new_itr = IXGBE_8K_ITR;
+               new_itr = IXGBE_12K_ITR;
                break;
        }