extern int amdgpu_emu_mode;
 extern uint amdgpu_smu_memory_pool_size;
 extern uint amdgpu_dc_feature_mask;
+extern uint amdgpu_dc_debug_mask;
 extern uint amdgpu_dm_abm_level;
 extern struct amdgpu_mgpu_info mgpu_info;
 extern int amdgpu_ras_enable;
 
 uint amdgpu_smu_memory_pool_size = 0;
 /* FBC (bit 0) disabled by default*/
 uint amdgpu_dc_feature_mask = 0;
+uint amdgpu_dc_debug_mask = 0;
 int amdgpu_async_gfx_ring = 1;
 int amdgpu_mcbp = 0;
 int amdgpu_discovery = -1;
 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
 
+/**
+ * DOC: dcdebugmask (uint)
+ * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
+ */
+MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
+module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
+
 /**
  * DOC: abmlevel (uint)
  * Override the default ABM (Adaptive Backlight Management) level used for DC
 
                goto error;
        }
 
+       if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
+               adev->dm.dc->debug.force_single_disp_pipe_split = false;
+               adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
+       }
+
+       if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
+               adev->dm.dc->debug.disable_stutter = true;
+
+       if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
+               adev->dm.dc->debug.disable_dsc = true;
+
+       if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
+               adev->dm.dc->debug.disable_clock_gate = true;
+
        r = dm_dmub_hw_init(adev);
        if (r) {
                DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
 
        DC_PSR_MASK = 0x8,
 };
 
+enum DC_DEBUG_MASK {
+       DC_DISABLE_PIPE_SPLIT = 0x1,
+       DC_DISABLE_STUTTER = 0x2,
+       DC_DISABLE_DSC = 0x4,
+       DC_DISABLE_CLOCK_GATING = 0x8
+};
+
 enum amd_dpm_forced_level;
 /**
  * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks