drm/amdgpu/sriov: skip programing some regs with new L1 policy

With new L1 policy, some regs are blocked at guest and they are
programed at host side. So skip programing the regs under sriov.

the regs are:
GCMC_VM_FB_LOCATION_TOP
GCMC_VM_FB_LOCATION_BASE
MMMC_VM_FB_LOCATION_TOP
MMMC_VM_FB_LOCATION_BASE
GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR
GCMC_VM_SYSTEM_APERTURE_LOW_ADDR
MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR
MMMC_VM_SYSTEM_APERTURE_LOW_ADDR
HDP_NONSURFACE_BASE
HDP_NONSURFACE_BASE_HI
GCMC_VM_AGP_TOP
GCMC_VM_AGP_BOT
GCMC_VM_AGP_BASE

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Tiecheng Zhou <Tiecheng.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index e0654a216ab5cb471f253cb00f740524fc66924e..cc866c36793946e5621630e6be0ec2a350f0b056 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -81,24 +81,31 @@ static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
 {
        uint64_t value;
 
-       /* Disable AGP. */
-       WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
-       WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0);
-       WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF);
-
-       /* Program the system aperture low logical page number. */
-       WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-                    adev->gmc.vram_start >> 18);
-       WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-                    adev->gmc.vram_end >> 18);
-
-       /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
-               + adev->vm_manager.vram_base_offset;
-       WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
-                    (u32)(value >> 12));
-       WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
-                    (u32)(value >> 44));
+       if (!amdgpu_sriov_vf(adev)) {
+               /*
+                * the new L1 policy will block SRIOV guest from writing
+                * these regs, and they will be programed at host.
+                * so skip programing these regs.
+                */
+               /* Disable AGP. */
+               WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
+               WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0);
+               WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF);
+
+               /* Program the system aperture low logical page number. */
+               WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
+                            adev->gmc.vram_start >> 18);
+               WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+                            adev->gmc.vram_end >> 18);
+
+               /* Set default page address. */
+               value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
+                       + adev->vm_manager.vram_base_offset;
+               WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
+                            (u32)(value >> 12));
+               WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+                            (u32)(value >> 44));
+       }
 
        /* Program "protection fault". */
        WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
@@ -260,18 +267,6 @@ static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev)
 
 int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev)
 {
-       if (amdgpu_sriov_vf(adev)) {
-               /*
-                * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
-                * VF copy registers so vbios post doesn't program them, for
-                * SRIOV driver need to program them
-                */
-               WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE,
-                            adev->gmc.vram_start >> 24);
-               WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP,
-                            adev->gmc.vram_end >> 24);
-       }
-
        /* GART Enable. */
        gfxhub_v2_0_init_gart_aperture_regs(adev);
        gfxhub_v2_0_init_system_aperture_regs(adev);

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index bde1896805219694c1927cbc9a57b39ad9c1fd8d..fb3f228458e5c282fbdd957937e96ebe526df4f6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -72,11 +72,18 @@ static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
        WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0);
        WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF);
 
-       /* Program the system aperture low logical page number. */
-       WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-                    adev->gmc.vram_start >> 18);
-       WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-                    adev->gmc.vram_end >> 18);
+       if (!amdgpu_sriov_vf(adev)) {
+               /*
+                * the new L1 policy will block SRIOV guest from writing
+                * these regs, and they will be programed at host.
+                * so skip programing these regs.
+                */
+               /* Program the system aperture low logical page number. */
+               WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
+                            adev->gmc.vram_start >> 18);
+               WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+                            adev->gmc.vram_end >> 18);
+       }
 
        /* Set default page address. */
        value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
@@ -247,18 +254,6 @@ static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
 
 int mmhub_v2_0_gart_enable(struct amdgpu_device *adev)
 {
-       if (amdgpu_sriov_vf(adev)) {
-               /*
-                * MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
-                * VF copy registers so vbios post doesn't program them, for
-                * SRIOV driver need to program them
-                */
-               WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE,
-                            adev->gmc.vram_start >> 24);
-               WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP,
-                            adev->gmc.vram_end >> 24);
-       }
-
        /* GART Enable. */
        mmhub_v2_0_init_gart_aperture_regs(adev);
        mmhub_v2_0_init_system_aperture_regs(adev);