drm/i915/xe2lpd: implement WA for underruns while enabling FBC

FIFO underruns are observed when FBC is enabled on plane 2 or
plane 3. Recommended WA is to update the FBC enabling sequence.
The plane binding register bits need to be updated separately
before programming the FBC enable bit.

Bspec: 74151
Reviewed-by: Mika Kahola <mika.kahola@intel.com> #v3
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231111114320.87277-2-vinod.govindapillai@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index bde12fe622750f046e01dc3dd34026c7bd8ffeb0..b73cf1c5ba33d62410693cbc213089a2cd862615 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -608,6 +608,7 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
 static void ivb_fbc_activate(struct intel_fbc *fbc)
 {
        struct drm_i915_private *i915 = fbc->i915;
+       u32 dpfc_ctl;
 
        if (DISPLAY_VER(i915) >= 10)
                glk_fbc_program_cfb_stride(fbc);
@@ -617,8 +618,13 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
        if (intel_gt_support_legacy_fencing(to_gt(i915)))
                snb_fbc_program_fence(fbc);
 
+       /* wa_14019417088 Alternative WA*/
+       dpfc_ctl = ivb_dpfc_ctl(fbc);
+       if (DISPLAY_VER(i915) >= 20)
+               intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
+
        intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
-                      DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
+                      DPFC_CTL_EN | dpfc_ctl);
 }
 
 static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)