select GENERIC_ISA_DMA
        select HAVE_PCSPKR_PLATFORM
        select IRQ_CPU
-       select IRQ_GIC
+       select MIPS_GIC
        select HW_HAS_PCI
        select I8253
        select I8259
        select CPU_MIPSR2_IRQ_EI
        select DMA_NONCOHERENT
        select IRQ_CPU
-       select IRQ_GIC
+       select MIPS_GIC
        select LIBFDT
        select MIPS_MSC
        select SYS_HAS_CPU_MIPS32_R1
 config IRQ_GT641XX
        bool
 
-config IRQ_GIC
-       select MIPS_CM
-       bool
-
 config PCI_GT64XXX_PCI0
        bool
 
 
 config CEVT_GIC
        bool "Use GIC global counter for clock events"
-       depends on IRQ_GIC && !MIPS_SEAD3
+       depends on MIPS_GIC && !MIPS_SEAD3
        help
          Use the GIC global counter for the clock events. The R4K clock
          event driver is always present, so if the platform ends up not
 
 obj-$(CONFIG_MIPS_MSC)         += irq-msc01.o
 obj-$(CONFIG_IRQ_TXX9)         += irq_txx9.o
 obj-$(CONFIG_IRQ_GT641XX)      += irq-gt641xx.o
-obj-$(CONFIG_IRQ_GIC)          += irq-gic.o
 
 obj-$(CONFIG_KPROBES)          += kprobes.o
 obj-$(CONFIG_32BIT)            += scall32-o32.o
 
  */
 static int c0_compare_int_pending(void)
 {
-#ifdef CONFIG_IRQ_GIC
+#ifdef CONFIG_MIPS_GIC
        if (cpu_has_veic)
                return gic_get_timer_pending();
 #endif
 
        unsigned long flags;
        int vpflags;
 
-#ifdef CONFIG_IRQ_GIC
+#ifdef CONFIG_MIPS_GIC
        if (gic_present) {
                gic_send_ipi_single(cpu, action);
                return;
 
 static void vsmp_init_secondary(void)
 {
-#ifdef CONFIG_IRQ_GIC
+#ifdef CONFIG_MIPS_GIC
        /* This is Malta specific: IPI,performance and timer interrupts */
        if (gic_present)
                change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
 
 {
        unsigned long flags;
        unsigned int count, start;
-#ifdef CONFIG_IRQ_GIC
+#ifdef CONFIG_MIPS_GIC
        unsigned int giccount = 0, gicstart = 0;
 #endif
 
 
        /* Initialize counters. */
        start = read_c0_count();
-#ifdef CONFIG_IRQ_GIC
+#ifdef CONFIG_MIPS_GIC
        if (gic_present)
                GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
 #endif
        while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 
        count = read_c0_count();
-#ifdef CONFIG_IRQ_GIC
+#ifdef CONFIG_MIPS_GIC
        if (gic_present)
                GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
 #endif
        count -= start;
        mips_hpt_frequency = count;
 
-#ifdef CONFIG_IRQ_GIC
+#ifdef CONFIG_MIPS_GIC
        if (gic_present) {
                giccount -= gicstart;
                gic_frequency = giccount;
        setup_pit_timer();
 #endif
 
-#ifdef CONFIG_IRQ_GIC
+#ifdef CONFIG_MIPS_GIC
        if (gic_present) {
                freq = freqround(gic_frequency, 5000);
                printk("GIC frequency %d.%02d MHz\n", freq/1000000,
 
        help
                Support for Texas Instruments Keystone 2 IRQ controller IP which
                is part of the Keystone 2 IPC mechanism
+
+config MIPS_GIC
+       bool
+       select MIPS_CM
 
 obj-$(CONFIG_BRCMSTB_L2_IRQ)           += irq-brcmstb-l2.o \
                                           irq-bcm7120-l2.o
 obj-$(CONFIG_KEYSTONE_IRQ)             += irq-keystone.o
+obj-$(CONFIG_MIPS_GIC)                 += irq-mips-gic.o