denali->host_write(denali, mode | 0x14000, 0x2400);
 }
 
-static void denali_setup_dma(struct denali_nand_info *denali,
-                            dma_addr_t dma_addr, int page, int write)
-{
-       if (denali->caps & DENALI_CAP_DMA_64BIT)
-               denali_setup_dma64(denali, dma_addr, page, write);
-       else
-               denali_setup_dma32(denali, dma_addr, page, write);
-}
-
 static int denali_pio_read(struct denali_nand_info *denali, void *buf,
                           size_t size, int page, int raw)
 {
        iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
 
        denali_reset_irq(denali);
-       denali_setup_dma(denali, dma_addr, page, write);
+       denali->setup_dma(denali, dma_addr, page, write);
 
        irq_status = denali_wait_for_irq(denali, irq_mask);
        if (!(irq_status & INTR__DMA_CMD_COMP))
        if (denali->dma_avail) {
                chip->options |= NAND_USE_BOUNCE_BUFFER;
                chip->buf_align = 16;
+               if (denali->caps & DENALI_CAP_DMA_64BIT)
+                       denali->setup_dma = denali_setup_dma64;
+               else
+                       denali->setup_dma = denali_setup_dma32;
        }
 
        chip->bbt_options |= NAND_BBT_USE_FLASH;
 
        const struct nand_ecc_caps *ecc_caps;
        u32 (*host_read)(struct denali_nand_info *denali, u32 addr);
        void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data);
+       void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr,
+                         int page, int write);
 };
 
 #define DENALI_CAP_HW_ECC_FIXUP                        BIT(0)