break;
                }
 
-               if (link->local_sink->edid_caps.panel_patch.disable_fec)
-                       link->ctx->dc->debug.disable_fec = true;
-
                // Check if edid is the same
                if ((prev_sink) &&
                    (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
        link_bw_kbps *= 8;   /* 8 bits per byte*/
        link_bw_kbps *= link_setting->lane_count;
 
-       if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec) {
+       if (dc_link_should_enable_fec(link)) {
                /* Account for FEC overhead.
                 * We have to do it based on caps,
                 * and not based on FEC being set ready,
                        !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
 }
 
+bool dc_link_should_enable_fec(const struct dc_link *link)
+{
+       bool is_fec_disable = false;
+       bool ret = false;
+
+       if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
+                       link->local_sink &&
+                       link->local_sink->edid_caps.panel_patch.disable_fec)
+               is_fec_disable = true;
+
+       if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)
+               ret = true;
+
+       return ret;
+}
 
        struct link_encoder *link_enc = link->link_enc;
        uint8_t fec_config = 0;
 
-       if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
+       if (!dc_link_should_enable_fec(link))
                return;
 
        if (link_enc->funcs->fec_set_ready &&
 {
        struct link_encoder *link_enc = link->link_enc;
 
-       if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
+       if (!dc_link_should_enable_fec(link))
                return;
 
        if (link_enc->funcs->fec_set_enable &&