u32 allow_update_cdf = 0;
        u32 sb_boundary_x_m1 = 0, sb_boundary_y_m1 = 0;
        int tile_info_base;
-       u32 tile_buf_pa;
+       u64 tile_buf_pa;
        u32 *tile_info_buf = instance->tile.va;
-       u32 pa = (u32)bs->dma_addr;
+       u64 pa = (u64)bs->dma_addr;
 
        if (uh->disable_cdf_update == 0)
                allow_update_cdf = 1;
                tile_info_buf[tile_info_base + 0] = (tile_group->tile_size[tile_num] << 3);
                tile_buf_pa = pa + tile_group->tile_start_offset[tile_num];
 
-               tile_info_buf[tile_info_base + 1] = (tile_buf_pa >> 4) << 4;
-               tile_info_buf[tile_info_base + 2] = (tile_buf_pa % 16) << 3;
+               /* save av1 tile high 4bits(bit 32-35) address in lower 4 bits position
+                * and clear original for hw requirement.
+                */
+               tile_info_buf[tile_info_base + 1] = (tile_buf_pa & 0xFFFFFFF0ull) |
+                       ((tile_buf_pa & 0xF00000000ull) >> 32);
+               tile_info_buf[tile_info_base + 2] = (tile_buf_pa & 0xFull) << 3;
 
                sb_boundary_x_m1 =
                        (tile->mi_col_starts[tile_col + 1] - tile->mi_col_starts[tile_col] - 1) &