i2c: twl: add register defines for pm master module

Some modules already need to talk to at least PROTECT_KEY
register, while at that, add defines to the entire register
space.

Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>

diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index 4793d8a7f48086e58bac27204e8245dcc40c558d..53089516c17a1d2d6a15b7dd9bfa5e1866f75ba3 100644 (file)
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -357,6 +357,52 @@ int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
 
 /*----------------------------------------------------------------------*/
 
+/*
+ * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER)
+ */
+
+#define TWL4030_PM_MASTER_CFG_P1_TRANSITION    0x00
+#define TWL4030_PM_MASTER_CFG_P2_TRANSITION    0x01
+#define TWL4030_PM_MASTER_CFG_P3_TRANSITION    0x02
+#define TWL4030_PM_MASTER_CFG_P123_TRANSITION  0x03
+#define TWL4030_PM_MASTER_STS_BOOT             0x04
+#define TWL4030_PM_MASTER_CFG_BOOT             0x05
+#define TWL4030_PM_MASTER_SHUNDAN              0x06
+#define TWL4030_PM_MASTER_BOOT_BCI             0x07
+#define TWL4030_PM_MASTER_CFG_PWRANA1          0x08
+#define TWL4030_PM_MASTER_CFG_PWRANA2          0x09
+#define TWL4030_PM_MASTER_BACKUP_MISC_STS      0x0b
+#define TWL4030_PM_MASTER_BACKUP_MISC_CFG      0x0c
+#define TWL4030_PM_MASTER_BACKUP_MISC_TST      0x0d
+#define TWL4030_PM_MASTER_PROTECT_KEY          0x0e
+#define TWL4030_PM_MASTER_STS_HW_CONDITIONS    0x0f
+#define TWL4030_PM_MASTER_P1_SW_EVENTS         0x10
+#define TWL4030_PM_MASTER_P2_SW_EVENTS         0x11
+#define TWL4030_PM_MASTER_P3_SW_EVENTS         0x12
+#define TWL4030_PM_MASTER_STS_P123_STATE       0x13
+#define TWL4030_PM_MASTER_PB_CFG               0x14
+#define TWL4030_PM_MASTER_PB_WORD_MSB          0x15
+#define TWL4030_PM_MASTER_PB_WORD_LSB          0x16
+#define TWL4030_PM_MASTER_SEQ_ADD_W2P          0x1c
+#define TWL4030_PM_MASTER_SEQ_ADD_P2A          0x1d
+#define TWL4030_PM_MASTER_SEQ_ADD_A2W          0x1e
+#define TWL4030_PM_MASTER_SEQ_ADD_A2S          0x1f
+#define TWL4030_PM_MASTER_SEQ_ADD_S2A12                0x20
+#define TWL4030_PM_MASTER_SEQ_ADD_S2A3         0x21
+#define TWL4030_PM_MASTER_SEQ_ADD_WARM         0x22
+#define TWL4030_PM_MASTER_MEMORY_ADDRESS       0x23
+#define TWL4030_PM_MASTER_MEMORY_DATA          0x24
+
+#define TWL4030_PM_MASTER_KEY_CFG1             0xc0
+#define TWL4030_PM_MASTER_KEY_CFG2             0x0c
+
+#define TWL4030_PM_MASTER_KEY_TST1             0xe0
+#define TWL4030_PM_MASTER_KEY_TST2             0x0e
+
+#define TWL4030_PM_MASTER_GLOBAL_TST           0xb6
+
+/*----------------------------------------------------------------------*/
+
 /* Power bus message definitions */
 
 /* The TWL4030/5030 splits its power-management resources (the various