clk: renesas: r9a07g04[34]: Use tabs instead of spaces

Use tabs instead of spaces in the CRU clock descriptions to match the
formatting used in the rest of the clock definitions.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250806092129.621194-5-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index f050f85659166ebeba023a58c28dd6e5dcd0aebf..33e9a1223c7214b39fec31a5f082899f380edf11 100644 (file)
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -213,13 +213,13 @@ static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
        DEF_MOD("sdhi1_aclk",   R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1,
                                0x554, 7, MSTOP(BUS_PERI_COM, BIT(1))),
 #ifdef CONFIG_ARM64
-       DEF_MOD("cru_sysclk",   R9A07G043_CRU_SYSCLK, CLK_M2_DIV2,
+       DEF_MOD("cru_sysclk",   R9A07G043_CRU_SYSCLK, CLK_M2_DIV2,
                                0x564, 0, MSTOP(BUS_PERI_VIDEO, BIT(3))),
-       DEF_MOD("cru_vclk",     R9A07G043_CRU_VCLK, R9A07G043_CLK_M2,
+       DEF_MOD("cru_vclk",     R9A07G043_CRU_VCLK, R9A07G043_CLK_M2,
                                0x564, 1, MSTOP(BUS_PERI_VIDEO, BIT(3))),
-       DEF_MOD("cru_pclk",     R9A07G043_CRU_PCLK, R9A07G043_CLK_ZT,
+       DEF_MOD("cru_pclk",     R9A07G043_CRU_PCLK, R9A07G043_CLK_ZT,
                                0x564, 2, MSTOP(BUS_PERI_VIDEO, BIT(3))),
-       DEF_MOD("cru_aclk",     R9A07G043_CRU_ACLK, R9A07G043_CLK_M0,
+       DEF_MOD("cru_aclk",     R9A07G043_CRU_ACLK, R9A07G043_CLK_M0,
                                0x564, 3, MSTOP(BUS_PERI_VIDEO, BIT(3))),
        DEF_COUPLED("lcdc_clk_a", R9A07G043_LCDC_CLK_A, R9A07G043_CLK_M0,
                                0x56c, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(8, 7))),

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index fdbc0635a869a1adf4880865d8767b9fb046ea2b..0dd264877b9a73ef8276248ce2d0842a1283a961 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -303,13 +303,13 @@ static const struct {
                                        0x558, 1, 0),
                DEF_MOD("gpu_ace_clk",  R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
                                        0x558, 2, 0),
-               DEF_MOD("cru_sysclk",   R9A07G044_CRU_SYSCLK, CLK_M2_DIV2,
+               DEF_MOD("cru_sysclk",   R9A07G044_CRU_SYSCLK, CLK_M2_DIV2,
                                        0x564, 0, MSTOP(BUS_PERI_VIDEO, BIT(3))),
-               DEF_MOD("cru_vclk",     R9A07G044_CRU_VCLK, R9A07G044_CLK_M2,
+               DEF_MOD("cru_vclk",     R9A07G044_CRU_VCLK, R9A07G044_CLK_M2,
                                        0x564, 1, MSTOP(BUS_PERI_VIDEO, BIT(3))),
-               DEF_MOD("cru_pclk",     R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT,
+               DEF_MOD("cru_pclk",     R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT,
                                        0x564, 2, MSTOP(BUS_PERI_VIDEO, BIT(3))),
-               DEF_MOD("cru_aclk",     R9A07G044_CRU_ACLK, R9A07G044_CLK_M0,
+               DEF_MOD("cru_aclk",     R9A07G044_CRU_ACLK, R9A07G044_CLK_M0,
                                        0x564, 3, MSTOP(BUS_PERI_VIDEO, BIT(3))),
                DEF_MOD("dsi_pll_clk",  R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,
                                        0x568, 0, MSTOP(BUS_PERI_VIDEO, GENMASK(6, 5))),