drm/i915: pass dev_priv explicitly to TRANS_VSYNCSHIFT

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_VSYNCSHIFT register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/8103a31fbf6da725e6aed3bb86c15bbd581164fb.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index b267099fde8a2764560ea759081be1105da2ee30..0625c4d5ee0b5ef99e518476f40a9687716adb5d 100644 (file)
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -982,7 +982,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
        if (is_vid_mode(intel_dsi)) {
                for_each_dsi_port(port, intel_dsi->ports) {
                        dsi_trans = dsi_port_to_transcoder(port);
-                       intel_de_write(dev_priv, TRANS_VSYNCSHIFT(dsi_trans),
+                       intel_de_write(dev_priv,
+                                      TRANS_VSYNCSHIFT(dev_priv, dsi_trans),
                                       vsync_shift);
                }
        }

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 49f7ac0f79979167be975cb2fdc035f954eb5a63..993eb0935f6b8b68b22169d7edd0a21fca15ed50 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2707,7 +2707,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
        }
 
        if (DISPLAY_VER(dev_priv) >= 4)
-               intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
+               intel_de_write(dev_priv,
+                              TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder),
                               vsyncshift);
 
        intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),

diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 9f8269705171ababeaee29ba009729fe5820c4c2..6a45bc1651c3249206b1e91a91a1c83791adb603 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -237,7 +237,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
        intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
                       intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder)));
        intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
-                      intel_de_read(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder)));
+                      intel_de_read(dev_priv, TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder)));
 }
 
 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 39f92739b8225aca8cafa41d9318c86bee6b4174..5f6f2bb06f35289bd48eba1c462f17f1529638de 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1143,7 +1143,7 @@
 #define TRANS_VBLANK(dev_priv, trans)  _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
 #define TRANS_VSYNC(dev_priv, trans)   _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
 #define BCLRPAT(dev_priv, trans)               _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
-#define TRANS_VSYNCSHIFT(trans)        _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
+#define TRANS_VSYNCSHIFT(dev_priv, trans)      _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
 #define PIPESRC(pipe)          _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
 #define TRANS_MULT(trans)      _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
 

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 5e1ef52922cca993fed104131a181befbf869c75..5abae7df0bfecaae43e79e891172a5ba589e8666 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -238,7 +238,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A));
        MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A));
        MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A));
-       MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
+       MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_A));
        MMIO_D(PIPESRC(TRANSCODER_A));
        MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
        MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
@@ -247,7 +247,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B));
        MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B));
        MMIO_D(BCLRPAT(dev_priv, TRANSCODER_B));
-       MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
+       MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_B));
        MMIO_D(PIPESRC(TRANSCODER_B));
        MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
        MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
@@ -256,7 +256,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C));
        MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C));
        MMIO_D(BCLRPAT(dev_priv, TRANSCODER_C));
-       MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
+       MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_C));
        MMIO_D(PIPESRC(TRANSCODER_C));
        MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
        MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
@@ -265,7 +265,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP));
        MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP));
        MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP));
-       MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP));
+       MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP));
        MMIO_D(PIPE_DATA_M1(TRANSCODER_A));
        MMIO_D(PIPE_DATA_N1(TRANSCODER_A));
        MMIO_D(PIPE_DATA_M2(TRANSCODER_A));