drm/amdgpu/vcn: Allow limiting ctx to instance 0 for AV1 at any time

There is no reason to require this to happen on first submitted IB only.
We need to wait for the queue to be idle, but it can be done at any
time (including when there are multiple video sessions active).

Signed-off-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 95173156f956aa1aab9b717abf322183b1ce0c16..f3085137ba08b924f4effb7ba5375b44c5a745ef 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -1886,15 +1886,19 @@ static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p,
                                struct amdgpu_job *job)
 {
        struct drm_gpu_scheduler **scheds;
-
-       /* The create msg must be in the first IB submitted */
-       if (atomic_read(&job->base.entity->fence_seq))
-               return -EINVAL;
+       struct dma_fence *fence;
 
        /* if VCN0 is harvested, we can't support AV1 */
        if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
                return -EINVAL;
 
+       /* wait for all jobs to finish before switching to instance 0 */
+       fence = amdgpu_ctx_get_fence(p->ctx, job->base.entity, ~0ull);
+       if (fence) {
+               dma_fence_wait(fence, false);
+               dma_fence_put(fence);
+       }
+
        scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC]
                [AMDGPU_RING_PRIO_DEFAULT].sched;
        drm_sched_entity_modify_sched(job->base.entity, scheds, 1);

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 8d20ae5bdb86d9d3f9e29b992dca8d26f9a456c8..bc9dfe5ffea714b09da2de87b24d46954962e77a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1804,15 +1804,19 @@ static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p,
                                struct amdgpu_job *job)
 {
        struct drm_gpu_scheduler **scheds;
-
-       /* The create msg must be in the first IB submitted */
-       if (atomic_read(&job->base.entity->fence_seq))
-               return -EINVAL;
+       struct dma_fence *fence;
 
        /* if VCN0 is harvested, we can't support AV1 */
        if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
                return -EINVAL;
 
+       /* wait for all jobs to finish before switching to instance 0 */
+       fence = amdgpu_ctx_get_fence(p->ctx, job->base.entity, ~0ull);
+       if (fence) {
+               dma_fence_wait(fence, false);
+               dma_fence_put(fence);
+       }
+
        scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC]
                [AMDGPU_RING_PRIO_0].sched;
        drm_sched_entity_modify_sched(job->base.entity, scheds, 1);