x86/mce: Use mce_rdmsrl() in severity checking code

MCA has its own special MSR accessors. Use them.

No functional changes.

Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20211208111343.8130-4-bp@alien8.de

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index f15efa242f44deeb1dbbd9584ce7eb34ca88c6e5..87a277fc80b42d279fb95c87cc87a7bc00c823ec 100644 (file)
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -362,7 +362,7 @@ void ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr)
 }
 
 /* MSR access wrappers used for error injection */
-static noinstr u64 mce_rdmsrl(u32 msr)
+noinstr u64 mce_rdmsrl(u32 msr)
 {
        DECLARE_ARGS(val, low, high);
 

diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h
index acd61c41846c424d611c6edd05907ae34c5e2d84..52c633950b38dbd8d82cc041fcc5d46a865a719f 100644 (file)
--- a/arch/x86/kernel/cpu/mce/internal.h
+++ b/arch/x86/kernel/cpu/mce/internal.h
@@ -207,4 +207,6 @@ static inline void pentium_machine_check(struct pt_regs *regs) {}
 static inline void winchip_machine_check(struct pt_regs *regs) {}
 #endif
 
+noinstr u64 mce_rdmsrl(u32 msr);
+
 #endif /* __X86_MCE_INTERNAL_H__ */

diff --git a/arch/x86/kernel/cpu/mce/severity.c b/arch/x86/kernel/cpu/mce/severity.c
index bb019a594a2c98d3e799b750eab63d59b61d602b..00e97ebbd94a31943f7ad74be021386a69f67dfd 100644 (file)
--- a/arch/x86/kernel/cpu/mce/severity.c
+++ b/arch/x86/kernel/cpu/mce/severity.c
@@ -288,8 +288,7 @@ static int error_context(struct mce *m, struct pt_regs *regs)
 
 static int mce_severity_amd_smca(struct mce *m, enum context err_ctx)
 {
-       u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
-       u32 low, high;
+       u64 mcx_cfg;
 
        /*
         * We need to look at the following bits:
@@ -300,11 +299,10 @@ static int mce_severity_amd_smca(struct mce *m, enum context err_ctx)
        if (!mce_flags.succor)
                return MCE_PANIC_SEVERITY;
 
-       if (rdmsr_safe(addr, &low, &high))
-               return MCE_PANIC_SEVERITY;
+       mcx_cfg = mce_rdmsrl(MSR_AMD64_SMCA_MCx_CONFIG(m->bank));
 
        /* TCC (Task context corrupt). If set and if IN_KERNEL, panic. */
-       if ((low & MCI_CONFIG_MCAX) &&
+       if ((mcx_cfg & MCI_CONFIG_MCAX) &&
            (m->status & MCI_STATUS_TCC) &&
            (err_ctx == IN_KERNEL))
                return MCE_PANIC_SEVERITY;