drm/vc4: hdmi: Support 2712 D-step register map

The D-step has increased FIFO sizes of the MAI_THR blocks,
resulting in changes to the register masking. Add support for
it.

Reviewed-by: Maxime Ripard <mripard@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20241025-drm-vc4-2712-support-v2-25-35efa83c8fc0@raspberrypi.com
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 1456966732ec36a4b3385b1080d1b622a2589f41..b9fc4d981cf4d682bedd978795cf7284d2650e74 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -2123,18 +2123,33 @@ static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
                                             VC4_HDMI_AUDIO_PACKET_CEA_MASK);
 
        /* Set the MAI threshold */
-       if (vc4->gen >= VC4_GEN_5)
+       switch (vc4->gen) {
+       case VC4_GEN_6_D:
+               HDMI_WRITE(HDMI_MAI_THR,
+                          VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICHIGH) |
+                          VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICLOW) |
+                          VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQHIGH) |
+                          VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQLOW));
+               break;
+       case VC4_GEN_6_C:
+       case VC4_GEN_5:
                HDMI_WRITE(HDMI_MAI_THR,
                           VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
                           VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
                           VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) |
                           VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW));
-       else
+               break;
+       case VC4_GEN_4:
                HDMI_WRITE(HDMI_MAI_THR,
                           VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) |
                           VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) |
                           VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) |
                           VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW));
+               break;
+       default:
+               drm_err(drm, "Unknown VC4 generation: %d", vc4->gen);
+               break;
+       }
 
        HDMI_WRITE(HDMI_MAI_CONFIG,
                   VC4_HDMI_MAI_CONFIG_BIT_REVERSE |

diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 0046bdb7ca32f2829fe598a0479ee114b9129a22..27158be19952c8a17ad97ab31643055c01098775 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -987,6 +987,15 @@ enum {
 # define VC4_HD_MAI_THR_DREQLOW_MASK           VC4_MASK(5, 0)
 # define VC4_HD_MAI_THR_DREQLOW_SHIFT          0
 
+# define VC6_D_HD_MAI_THR_PANICHIGH_MASK       VC4_MASK(29, 23)
+# define VC6_D_HD_MAI_THR_PANICHIGH_SHIFT      23
+# define VC6_D_HD_MAI_THR_PANICLOW_MASK                VC4_MASK(21, 15)
+# define VC6_D_HD_MAI_THR_PANICLOW_SHIFT       15
+# define VC6_D_HD_MAI_THR_DREQHIGH_MASK                VC4_MASK(13, 7)
+# define VC6_D_HD_MAI_THR_DREQHIGH_SHIFT       7
+# define VC6_D_HD_MAI_THR_DREQLOW_MASK         VC4_MASK(6, 0)
+# define VC6_D_HD_MAI_THR_DREQLOW_SHIFT                0
+
 /* Divider from HDMI HSM clock to MAI serial clock.  Sampling period
  * converges to N / (M + 1) cycles.
  */