drm/i915: Move skl+ wm/ddb registers to proper headers

On SKL+ the watermark/DDB registers are proper per-plane
registers. Move the definitons to their respective files.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 62f7fb5c3f1044b1d02116d75990c5590fb5a802..a478ef5787c5605e7791ca19c7a01f03d9303544 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -75,4 +75,24 @@
 #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
 #define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
 
+/* skl+ */
+#define _CUR_WM_A_0            0x70140
+#define _CUR_WM_B_0            0x71140
+#define _CUR_WM_SAGV_A         0x70158
+#define _CUR_WM_SAGV_B         0x71158
+#define _CUR_WM_SAGV_TRANS_A   0x7015C
+#define _CUR_WM_SAGV_TRANS_B   0x7115C
+#define _CUR_WM_TRANS_A                0x70168
+#define _CUR_WM_TRANS_B                0x71168
+#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
+#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
+#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
+#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
+#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
+
+/* skl+ */
+#define _CUR_BUF_CFG_A                         0x7017c
+#define _CUR_BUF_CFG_B                         0x7117c
+#define CUR_BUF_CFG(pipe)      _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
+
 #endif /* __INTEL_CURSOR_REGS_H__ */

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 7e34470beb747dfdc38731dbede36473a91f16da..2222d0c760e83072b9513a76467dd896d874fa92 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -402,4 +402,68 @@
                                                            (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
                                                            (index) * 4)
 
+#define _PLANE_WM_1_A_0                0x70240
+#define _PLANE_WM_1_B_0                0x71240
+#define _PLANE_WM_2_A_0                0x70340
+#define _PLANE_WM_2_B_0                0x71340
+#define _PLANE_WM_SAGV_1_A     0x70258
+#define _PLANE_WM_SAGV_1_B     0x71258
+#define _PLANE_WM_SAGV_2_A     0x70358
+#define _PLANE_WM_SAGV_2_B     0x71358
+#define _PLANE_WM_SAGV_TRANS_1_A       0x7025C
+#define _PLANE_WM_SAGV_TRANS_1_B       0x7125C
+#define _PLANE_WM_SAGV_TRANS_2_A       0x7035C
+#define _PLANE_WM_SAGV_TRANS_2_B       0x7135C
+#define _PLANE_WM_TRANS_1_A    0x70268
+#define _PLANE_WM_TRANS_1_B    0x71268
+#define _PLANE_WM_TRANS_2_A    0x70368
+#define _PLANE_WM_TRANS_2_B    0x71368
+#define   PLANE_WM_EN          (1 << 31)
+#define   PLANE_WM_IGNORE_LINES        (1 << 30)
+#define   PLANE_WM_LINES_MASK  REG_GENMASK(26, 14)
+#define   PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
+
+#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
+#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
+#define _PLANE_WM_BASE(pipe, plane) \
+       _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
+#define PLANE_WM(pipe, plane, level) \
+       _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
+#define _PLANE_WM_SAGV_1(pipe) \
+       _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
+#define _PLANE_WM_SAGV_2(pipe) \
+       _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
+#define PLANE_WM_SAGV(pipe, plane) \
+       _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
+#define _PLANE_WM_SAGV_TRANS_1(pipe) \
+       _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
+#define _PLANE_WM_SAGV_TRANS_2(pipe) \
+       _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
+#define PLANE_WM_SAGV_TRANS(pipe, plane) \
+       _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
+#define _PLANE_WM_TRANS_1(pipe) \
+       _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
+#define _PLANE_WM_TRANS_2(pipe) \
+       _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
+#define PLANE_WM_TRANS(pipe, plane) \
+       _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
+
+#define _PLANE_BUF_CFG_1_B                     0x7127c
+#define _PLANE_BUF_CFG_2_B                     0x7137c
+#define _PLANE_BUF_CFG_1(pipe) \
+       _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
+#define _PLANE_BUF_CFG_2(pipe) \
+       _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
+#define PLANE_BUF_CFG(pipe, plane)     \
+       _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
+
+#define _PLANE_NV12_BUF_CFG_1_B                0x71278
+#define _PLANE_NV12_BUF_CFG_2_B                0x71378
+#define _PLANE_NV12_BUF_CFG_1(pipe)    \
+       _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
+#define _PLANE_NV12_BUF_CFG_2(pipe)    \
+       _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
+#define PLANE_NV12_BUF_CFG(pipe, plane)        \
+       _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
+
 #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 53a565c673e268a6332f611aaa7285c7ff7baad1..2a2073bf3aca0e6e26f935ef9723fd0c8180086a 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -13,6 +13,7 @@
 #include "intel_bw.h"
 #include "intel_cdclk.h"
 #include "intel_crtc.h"
+#include "intel_cursor_regs.h"
 #include "intel_de.h"
 #include "intel_display.h"
 #include "intel_display_power.h"

diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
index 269163fa33508e9354057a4053576f425f69088b..c5572fc0e847c60d27aefdf7c8b94d5acb2d3e5a 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
@@ -43,89 +43,6 @@
 #define   MBUS_TRANSLATION_THROTTLE_MIN_MASK   REG_GENMASK(15, 13)
 #define   MBUS_TRANSLATION_THROTTLE_MIN(val)   REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
 
-/* Watermark register definitions for SKL */
-#define _CUR_WM_A_0            0x70140
-#define _CUR_WM_B_0            0x71140
-#define _CUR_WM_SAGV_A         0x70158
-#define _CUR_WM_SAGV_B         0x71158
-#define _CUR_WM_SAGV_TRANS_A   0x7015C
-#define _CUR_WM_SAGV_TRANS_B   0x7115C
-#define _CUR_WM_TRANS_A                0x70168
-#define _CUR_WM_TRANS_B                0x71168
-#define _PLANE_WM_1_A_0                0x70240
-#define _PLANE_WM_1_B_0                0x71240
-#define _PLANE_WM_2_A_0                0x70340
-#define _PLANE_WM_2_B_0                0x71340
-#define _PLANE_WM_SAGV_1_A     0x70258
-#define _PLANE_WM_SAGV_1_B     0x71258
-#define _PLANE_WM_SAGV_2_A     0x70358
-#define _PLANE_WM_SAGV_2_B     0x71358
-#define _PLANE_WM_SAGV_TRANS_1_A       0x7025C
-#define _PLANE_WM_SAGV_TRANS_1_B       0x7125C
-#define _PLANE_WM_SAGV_TRANS_2_A       0x7035C
-#define _PLANE_WM_SAGV_TRANS_2_B       0x7135C
-#define _PLANE_WM_TRANS_1_A    0x70268
-#define _PLANE_WM_TRANS_1_B    0x71268
-#define _PLANE_WM_TRANS_2_A    0x70368
-#define _PLANE_WM_TRANS_2_B    0x71368
-#define   PLANE_WM_EN          (1 << 31)
-#define   PLANE_WM_IGNORE_LINES        (1 << 30)
-#define   PLANE_WM_LINES_MASK  REG_GENMASK(26, 14)
-#define   PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
-
-#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
-#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
-#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
-#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
-#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
-#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
-#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
-#define _PLANE_WM_BASE(pipe, plane) \
-       _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
-#define PLANE_WM(pipe, plane, level) \
-       _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
-#define _PLANE_WM_SAGV_1(pipe) \
-       _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
-#define _PLANE_WM_SAGV_2(pipe) \
-       _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
-#define PLANE_WM_SAGV(pipe, plane) \
-       _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
-#define _PLANE_WM_SAGV_TRANS_1(pipe) \
-       _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
-#define _PLANE_WM_SAGV_TRANS_2(pipe) \
-       _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
-#define PLANE_WM_SAGV_TRANS(pipe, plane) \
-       _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
-#define _PLANE_WM_TRANS_1(pipe) \
-       _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
-#define _PLANE_WM_TRANS_2(pipe) \
-       _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
-#define PLANE_WM_TRANS(pipe, plane) \
-       _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
-
-#define _PLANE_BUF_CFG_1_B                     0x7127c
-#define _PLANE_BUF_CFG_2_B                     0x7137c
-#define _PLANE_BUF_CFG_1(pipe) \
-       _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
-#define _PLANE_BUF_CFG_2(pipe) \
-       _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
-#define PLANE_BUF_CFG(pipe, plane)     \
-       _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
-
-#define _PLANE_NV12_BUF_CFG_1_B                0x71278
-#define _PLANE_NV12_BUF_CFG_2_B                0x71378
-#define _PLANE_NV12_BUF_CFG_1(pipe)    \
-       _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
-#define _PLANE_NV12_BUF_CFG_2(pipe)    \
-       _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
-#define PLANE_NV12_BUF_CFG(pipe, plane)        \
-       _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
-
-/* SKL new cursor registers */
-#define _CUR_BUF_CFG_A                         0x7017c
-#define _CUR_BUF_CFG_B                         0x7117c
-#define CUR_BUF_CFG(pipe)      _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
-
 /*
  * The below are numbered starting from "S1" on gen11/gen12, but starting
  * with display 13, the bspec switches to a 0-based numbering scheme

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index aae0443015f0bf37eabe6e6b5a347d8f6940b0b1..6c857beb508396c752f57c6c989f31bc2dcd2c5e 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -42,6 +42,7 @@
 #include "i915_pvinfo.h"
 #include "intel_mchbar_regs.h"
 #include "display/bxt_dpio_phy_regs.h"
+#include "display/intel_cursor_regs.h"
 #include "display/intel_display_types.h"
 #include "display/intel_dmc_regs.h"
 #include "display/intel_dp_aux_regs.h"