#define ENA_REGS_ADMIN_INTR_MASK 1
 
+#define ENA_POLL_MS    5
+
 /*****************************************************************************/
 /*****************************************************************************/
 /*****************************************************************************/
                        goto err;
                }
 
-               msleep(100);
+               msleep(ENA_POLL_MS);
        }
 
        if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
 {
        u32 val, i;
 
+       /* Convert timeout from resolution of 100ms to ENA_POLL_MS */
+       timeout = (timeout * 100) / ENA_POLL_MS;
+
        for (i = 0; i < timeout; i++) {
                val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
 
                        exp_state)
                        return 0;
 
-               /* The resolution of the timeout is 100ms */
-               msleep(100);
+               msleep(ENA_POLL_MS);
        }
 
        return -ETIME;
        spin_lock_irqsave(&admin_queue->q_lock, flags);
        while (atomic_read(&admin_queue->outstanding_cmds) != 0) {
                spin_unlock_irqrestore(&admin_queue->q_lock, flags);
-               msleep(20);
+               msleep(ENA_POLL_MS);
                spin_lock_irqsave(&admin_queue->q_lock, flags);
        }
        spin_unlock_irqrestore(&admin_queue->q_lock, flags);