drm/i915: Don't wait for PCH on reset

BIOS should be setting this, but in case it doesn't...

v2: Define the bits we actually want to clear (Jesse)
Make it an RMW op (Jesse)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 911bd40ef5132949f49e0c9f15d569577b18c372..74c5601502939a754d95e1f9711f98596bc655a0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3992,6 +3992,12 @@ i915_gem_init_hw(struct drm_device *dev)
        if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
                I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
 
+       if (HAS_PCH_NOP(dev)) {
+               u32 temp = I915_READ(GEN7_MSG_CTL);
+               temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
+               I915_WRITE(GEN7_MSG_CTL, temp);
+       }
+
        i915_gem_l3_remap(dev);
 
        i915_gem_init_swizzling(dev);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058686c0dbbf6e4f4da3f163a08f4a7f8a25dde4..0e4b7fb7d6913c44ef8fc56e7fa616ea68fe6867 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3568,6 +3568,9 @@
 #define DISP_ARB_CTL   0x45000
 #define  DISP_TILE_SURFACE_SWIZZLING   (1<<13)
 #define  DISP_FBC_WM_DIS               (1<<15)
+#define GEN7_MSG_CTL   0x45010
+#define  WAIT_FOR_PCH_RESET_ACK                (1<<1)
+#define  WAIT_FOR_PCH_FLR_ACK          (1<<0)
 
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1             0x7010