]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
x86/pti: Do not enable PTI on CPUs which are not vulnerable to Meltdown
authorDavid Woodhouse <dwmw@amazon.co.uk>
Thu, 25 Jan 2018 16:14:13 +0000 (16:14 +0000)
committerJack Vogel <jack.vogel@oracle.com>
Thu, 8 Feb 2018 18:15:58 +0000 (10:15 -0800)
Also, for CPUs which don't speculate at all, don't report that they're
vulnerable to the Spectre variants either.

Leave the cpu_no_meltdown[] match table with just X86_VENDOR_AMD in it
for now, even though that could be done with a simple comparison, on the
assumption that we'll have more to add.

Based on suggestions from Dave Hansen and Alan Cox.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Borislav Petkov <bp@suse.de>
Acked-by: Dave Hansen <dave.hansen@intel.com>
Cc: gnomes@lxorguk.ukuu.org.uk
Cc: ak@linux.intel.com
Cc: ashok.raj@intel.com
Cc: karahmed@amazon.de
Cc: arjan@linux.intel.com
Cc: torvalds@linux-foundation.org
Cc: peterz@infradead.org
Cc: bp@alien8.de
Cc: pbonzini@redhat.com
Cc: tim.c.chen@linux.intel.com
Cc: gregkh@linux-foundation.org
Link: https://lkml.kernel.org/r/1516896855-7642-6-git-send-email-dwmw@amazon.co.uk
(cherry picked from commit fec9434a12f38d3aeafeb75711b71d8a1fdef621)

Orabug: 27477743
CVE: CVE-2017-5715

[Backport:
 s/X86_FEATURE_ARCH_CAPABILITIES/X86_FEATURE_IA32_ARCH_CAPS/
 Fix compiler warnings by removing __init/__initdata from
   cpu_no_speculation, cpu_no_meltdown, and cpu_vulnerable_to_meltdown
]
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Pavel Tatashin <pasha.tatashin@oracle.com>
arch/x86/kernel/cpu/common.c

index 892972ff4137e7a50888eb259023a5dbd350bc06..39876a3c26caaca8931ef1eb87da8a7cff5a972f 100644 (file)
@@ -42,6 +42,8 @@
 #include <asm/pat.h>
 #include <asm/microcode.h>
 #include <asm/microcode_intel.h>
+#include <asm/intel-family.h>
+#include <asm/cpu_device_id.h>
 
 #ifdef CONFIG_X86_LOCAL_APIC
 #include <asm/uv/uv.h>
@@ -799,6 +801,41 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
 #endif
 }
 
+static const struct x86_cpu_id cpu_no_speculation[] = {
+       { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_CEDARVIEW,   X86_FEATURE_ANY },
+       { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_CLOVERVIEW,  X86_FEATURE_ANY },
+       { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_LINCROFT,    X86_FEATURE_ANY },
+       { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_PENWELL,     X86_FEATURE_ANY },
+       { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_PINEVIEW,    X86_FEATURE_ANY },
+       { X86_VENDOR_CENTAUR,   5 },
+       { X86_VENDOR_INTEL,     5 },
+       { X86_VENDOR_NSC,       5 },
+       { X86_VENDOR_ANY,       4 },
+       {}
+};
+
+static const struct x86_cpu_id cpu_no_meltdown[] = {
+       { X86_VENDOR_AMD },
+       {}
+};
+
+static bool cpu_vulnerable_to_meltdown(struct cpuinfo_x86 *c)
+{
+       u64 ia32_cap = 0;
+
+       if (x86_match_cpu(cpu_no_meltdown))
+               return false;
+
+       if (cpu_has(c, X86_FEATURE_IA32_ARCH_CAPS))
+               rdmsrl(X86_FEATURE_IA32_ARCH_CAPS, ia32_cap);
+
+       /* Rogue Data Cache Load? No! */
+       if (ia32_cap & ARCH_CAP_RDCL_NO)
+               return false;
+
+       return true;
+}
+
 /*
  * Do minimum CPU detection early.
  * Fields really needed: vendor, cpuid_level, family, model, mask,
@@ -1082,12 +1119,13 @@ static void identify_cpu(struct cpuinfo_x86 *c)
 #ifdef CONFIG_NUMA
        numa_add_cpu(smp_processor_id());
 #endif
+       if (!x86_match_cpu(cpu_no_speculation)) {
+               if (cpu_vulnerable_to_meltdown(c))
+                       setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
+               setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
+               setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
+       }
 
-       if (c->x86_vendor != X86_VENDOR_AMD)
-               setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
-
-       setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
-       setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
 }
 
 /*