name = "Tremont";
                break;
 
-       case INTEL_FAM6_ALDERLAKE_N:
+       case INTEL_FAM6_ATOM_GRACEMONT:
                x86_pmu.mid_ack = true;
                memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
                       sizeof(hw_cache_event_ids));
 
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,      &glm_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,        &glm_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,      &glm_cstates),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,      &adl_cstates),
 
        X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,           &icl_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(ICELAKE,             &icl_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,          &icl_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           &adl_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         &adl_cstates),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,         &adl_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,          &adl_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,        &adl_cstates),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S,        &adl_cstates),
 
        X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,          &rkl_uncore_init),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           &adl_uncore_init),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         &adl_uncore_init),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,         &adl_uncore_init),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,          &adl_uncore_init),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,        &adl_uncore_init),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S,        &adl_uncore_init),
        X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,    &spr_uncore_init),
        X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,     &spr_uncore_init),
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,      &snr_uncore_init),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,      &adl_uncore_init),
        {},
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_uncore_match);
 
        case INTEL_FAM6_ROCKETLAKE:
        case INTEL_FAM6_ALDERLAKE:
        case INTEL_FAM6_ALDERLAKE_L:
-       case INTEL_FAM6_ALDERLAKE_N:
+       case INTEL_FAM6_ATOM_GRACEMONT:
        case INTEL_FAM6_RAPTORLAKE:
        case INTEL_FAM6_RAPTORLAKE_P:
        case INTEL_FAM6_RAPTORLAKE_S:
 
        X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,           &model_skl),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           &model_skl),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         &model_skl),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,         &model_skl),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,      &model_skl),
        X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,    &model_spr),
        X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,     &model_spr),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,          &model_skl),
 
 
 #define INTEL_FAM6_ALDERLAKE           0x97    /* Golden Cove / Gracemont */
 #define INTEL_FAM6_ALDERLAKE_L         0x9A    /* Golden Cove / Gracemont */
-#define INTEL_FAM6_ALDERLAKE_N         0xBE
 
 #define INTEL_FAM6_RAPTORLAKE          0xB7
 #define INTEL_FAM6_RAPTORLAKE_P                0xBA
 #define INTEL_FAM6_ATOM_TREMONT                0x96 /* Elkhart Lake */
 #define INTEL_FAM6_ATOM_TREMONT_L      0x9C /* Jasper Lake */
 
+#define INTEL_FAM6_ATOM_GRACEMONT      0xBE /* Alderlake N */
+
 #define INTEL_FAM6_SIERRAFOREST_X      0xAF
 
 #define INTEL_FAM6_GRANDRIDGE          0xB6
 
 static const struct x86_cpu_id intel_epb_normal[] = {
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,
                                   ENERGY_PERF_BIAS_NORMAL_POWERSAVE),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,
                                   ENERGY_PERF_BIAS_NORMAL_POWERSAVE),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,
                                   ENERGY_PERF_BIAS_NORMAL_POWERSAVE),
 
 static const struct x86_cpu_id invlpg_miss_ids[] = {
        INTEL_MATCH(INTEL_FAM6_ALDERLAKE   ),
        INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ),
-       INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ),
+       INTEL_MATCH(INTEL_FAM6_ATOM_GRACEMONT ),
        INTEL_MATCH(INTEL_FAM6_RAPTORLAKE  ),
        INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P),
        INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S),
 
                .enter = NULL }
 };
 
-static struct cpuidle_state adl_n_cstates[] __initdata = {
+static struct cpuidle_state gmt_cstates[] __initdata = {
        {
                .name = "C1",
                .desc = "MWAIT 0x00",
        .state_table = adl_l_cstates,
 };
 
-static const struct idle_cpu idle_cpu_adl_n __initconst = {
-       .state_table = adl_n_cstates,
+static const struct idle_cpu idle_cpu_gmt __initconst = {
+       .state_table = gmt_cstates,
 };
 
 static const struct idle_cpu idle_cpu_spr __initconst = {
        X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,           &idle_cpu_icx),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           &idle_cpu_adl),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         &idle_cpu_adl_l),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,         &idle_cpu_adl_n),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,      &idle_cpu_gmt),
        X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,    &idle_cpu_spr),
        X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,     &idle_cpu_spr),
        X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL,        &idle_cpu_knl),
                break;
        case INTEL_FAM6_ALDERLAKE:
        case INTEL_FAM6_ALDERLAKE_L:
-       case INTEL_FAM6_ALDERLAKE_N:
+       case INTEL_FAM6_ATOM_GRACEMONT:
                adl_idle_state_table_update();
                break;
        }
 
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,      icl_core_init),
        X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,          tgl_core_init),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         tgl_core_init),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,         tgl_core_init),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,      tgl_core_init),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           adl_core_init),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,        tgl_core_init),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,          adl_core_init),
 
        X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,          &rapl_defaults_core),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           &rapl_defaults_core),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         &rapl_defaults_core),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,         &rapl_defaults_core),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,      &rapl_defaults_core),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,          &rapl_defaults_core),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,        &rapl_defaults_core),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S,        &rapl_defaults_core),
 
        X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, NULL),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, NULL),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE, NULL),
 
        X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, NULL),
-       X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, NULL),
+       X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, NULL),
        X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, NULL),
 
        case INTEL_FAM6_LAKEFIELD:
        case INTEL_FAM6_ALDERLAKE:
        case INTEL_FAM6_ALDERLAKE_L:
-       case INTEL_FAM6_ALDERLAKE_N:
+       case INTEL_FAM6_ATOM_GRACEMONT:
        case INTEL_FAM6_RAPTORLAKE:
        case INTEL_FAM6_RAPTORLAKE_P:
        case INTEL_FAM6_RAPTORLAKE_S: