It's related to the memory manager so move it there.
v2: inline the structure
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
        struct amdgpu_atcs_functions functions;
 };
 
-/*
- * Firmware VRAM reservation
- */
-struct amdgpu_fw_vram_usage {
-       u64 start_offset;
-       u64 size;
-       struct amdgpu_bo *reserved_bo;
-       void *va;
-};
-
 /*
  * CGS
  */
        struct delayed_work     delayed_init_work;
 
        struct amdgpu_virt      virt;
-       /* firmware VRAM reservation */
-       struct amdgpu_fw_vram_usage fw_vram_usage;
 
        /* link all shadow bo */
        struct list_head                shadow_list;
 
                        (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
                        ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
                        /* Firmware request VRAM reservation for SR-IOV */
-                       adev->fw_vram_usage.start_offset = (start_addr &
+                       adev->mman.fw_vram_usage_start_offset = (start_addr &
                                (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
-                       adev->fw_vram_usage.size = size << 10;
+                       adev->mman.fw_vram_usage_size = size << 10;
                        /* Use the default scratch size */
                        usage_bytes = 0;
                } else {
 
                        (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
                        ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
                        /* Firmware request VRAM reservation for SR-IOV */
-                       adev->fw_vram_usage.start_offset = (start_addr &
+                       adev->mman.fw_vram_usage_start_offset = (start_addr &
                                (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
-                       adev->fw_vram_usage.size = size << 10;
+                       adev->mman.fw_vram_usage_size = size << 10;
                        /* Use the default scratch size */
                        usage_bytes = 0;
                } else {
 
  */
 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
 {
-       amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
-               NULL, &adev->fw_vram_usage.va);
+       amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
+               NULL, &adev->mman.fw_vram_usage_va);
 }
 
 /**
 {
        uint64_t vram_size = adev->gmc.visible_vram_size;
 
-       adev->fw_vram_usage.va = NULL;
-       adev->fw_vram_usage.reserved_bo = NULL;
+       adev->mman.fw_vram_usage_va = NULL;
+       adev->mman.fw_vram_usage_reserved_bo = NULL;
 
-       if (adev->fw_vram_usage.size == 0 ||
-           adev->fw_vram_usage.size > vram_size)
+       if (adev->mman.fw_vram_usage_size == 0 ||
+           adev->mman.fw_vram_usage_size > vram_size)
                return 0;
 
        return amdgpu_bo_create_kernel_at(adev,
-                                         adev->fw_vram_usage.start_offset,
-                                         adev->fw_vram_usage.size,
+                                         adev->mman.fw_vram_usage_start_offset,
+                                         adev->mman.fw_vram_usage_size,
                                          AMDGPU_GEM_DOMAIN_VRAM,
-                                         &adev->fw_vram_usage.reserved_bo,
-                                         &adev->fw_vram_usage.va);
+                                         &adev->mman.fw_vram_usage_reserved_bo,
+                                         &adev->mman.fw_vram_usage_va);
 }
 
 /*
 
        uint8_t                         *discovery_bin;
        uint32_t                        discovery_tmr_size;
        struct amdgpu_bo                *discovery_memory;
+
+       /* firmware VRAM reservation */
+       u64             fw_vram_usage_start_offset;
+       u64             fw_vram_usage_size;
+       struct amdgpu_bo        *fw_vram_usage_reserved_bo;
+       void            *fw_vram_usage_va;
 };
 
 struct amdgpu_copy_mem {
 
        if (bp_block_size) {
                bp_cnt = bp_block_size / sizeof(uint64_t);
                for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) {
-                       retired_page = *(uint64_t *)(adev->fw_vram_usage.va +
+                       retired_page = *(uint64_t *)(adev->mman.fw_vram_usage_va +
                                        bp_block_offset + bp_idx * sizeof(uint64_t));
                        bp.retired_page = retired_page;
 
        adev->virt.fw_reserve.p_pf2vf = NULL;
        adev->virt.fw_reserve.p_vf2pf = NULL;
 
-       if (adev->fw_vram_usage.va != NULL) {
+       if (adev->mman.fw_vram_usage_va != NULL) {
                adev->virt.fw_reserve.p_pf2vf =
                        (struct amd_sriov_msg_pf2vf_info_header *)(
-                       adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET);
+                       adev->mman.fw_vram_usage_va + AMDGIM_DATAEXCHANGE_OFFSET);
                AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size);
                AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum);
                AMDGPU_FW_VRAM_PF2VF_READ(adev, feature_flags, &adev->virt.gim_feature);