struct dc_plane_state *plane_state = pipe_ctx->plane_state;
        struct xfm_grph_csc_adjustment adjust;
        struct out_csc_color_matrix tbl_entry;
+#if defined(CONFIG_DRM_AMD_DC_FBC)
+       unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
+#endif
        unsigned int i;
        DC_LOGGER_INIT();
        memset(&tbl_entry, 0, sizeof(tbl_entry));
        program_scaler(dc, pipe_ctx);
 
 #if defined(CONFIG_DRM_AMD_DC_FBC)
-       if (dc->fbc_compressor && old_pipe->stream) {
+       /* fbc not applicable on Underlay pipe */
+       if (dc->fbc_compressor && old_pipe->stream &&
+           pipe_ctx->pipe_idx != underlay_idx) {
                if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
                        dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
                else