default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
        default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
        default 0xfef36000 if DEBUG_HIGHBANK_UART
 +      default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
 +      default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
 +      default 0xfefb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
        default 0xfefff700 if ARCH_IOP33X
        default 0xff003000 if DEBUG_U300_UART
+       default 0xffd01000 if DEBUG_HIP01_UART
        default DEBUG_UART_PHYS if !MMU
        depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
                DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
 -              DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
 +              DEBUG_MSM_UART || DEBUG_NETX_UART || \
 +              DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
-               DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART
+               DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART || \
+               DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0
  
  config DEBUG_UART_8250_SHIFT
        int "Register offset shift for the 8250 debug UART"
 
  #include <asm/mach/map.h>
  #include <asm/hardware/cache-l2x0.h>
  #include "core.h"
+ #include "pm.h"
  
 +#define RK3288_GRF_SOC_CON0 0x244
 +
 +static void __init rockchip_timer_init(void)
 +{
 +      if (of_machine_is_compatible("rockchip,rk3288")) {
 +              struct regmap *grf;
 +
 +              /*
 +               * Disable auto jtag/sdmmc switching that causes issues
 +               * with the mmc controllers making them unreliable
 +               */
 +              grf = syscon_regmap_lookup_by_compatible("rockchip,rk3288-grf");
 +              if (!IS_ERR(grf))
 +                      regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000);
 +              else
 +                      pr_err("rockchip: could not get grf syscon\n");
 +      }
 +
 +      of_clk_init(NULL);
 +      clocksource_of_init();
 +}
 +
  static void __init rockchip_dt_init(void)
  {
+       rockchip_suspend_init();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
        platform_device_register_simple("cpufreq-dt", 0, NULL, 0);
  }
        NULL,
  };
  
- DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
+ DT_MACHINE_START(ROCKCHIP_DT, "Rockchip (Device Tree)")
        .l2c_aux_val    = 0,
        .l2c_aux_mask   = ~0,
 +      .init_time      = rockchip_timer_init,
        .dt_compat      = rockchip_board_dt_compat,
        .init_machine   = rockchip_dt_init,
  MACHINE_END